Privacy amplification (PA) is an essential part in a quantum key distribution (QKD) system, distilling a highly secure key from a partially secure string by public negotiation between two parties. The optimization objectives of privacy amplification for QKD are large block size, high throughput and low cost. For the global optimization of these objectives, a novel privacy amplification algorithm is proposed in this paper by combining multilinear-modular-hashing and modular arithmetic hashing. This paper proves the security of this hybrid hashing PA algorithm within the framework of both information theory and composition security theory. A scheme based on this algorithm is implemented and evaluated on a CPU platform. The results on a typical CV-QKD system indicate that the throughput of this scheme (261Mbps@2.6*10^8 input block size) is twice higher than the best existing scheme (140Mbps@1*10^8 input block size). Moreover, This scheme is implemented on a mobile CPU platform instead of a desktop CPU or a server CPU, which means that this algorithm has a better performance with a much lower cost and power consumption.
In this paper, a high-performance field-programmable gate array (FPGA) based privacy amplification (PA) scheme for both continuous variable and discrete variable - quantum key distribution (QKD) is presented, which can provide more than 1.5 Gbps throughput at the input block size close to
108. Besides, the resource consumption is so economical that there is no need of any external storage. To the best of our knowledge, our scheme outperforms existing FPGA based PA schemes by over an order of magnitude in terms of throughput and input block size. To achieve this feature, we design a novel FPGA-based hybrid hash PA algorithm combining multilinear modular hash and modular arithmetic hash (MMH-MH) based on number theoretical transform (NTT). Based on the hybrid hash algorithm, many optimization strategies are designed in our FPGA based PA scheme, such as an NTT-based optimization unit, an NTT-reusable architecture, a memory-saving modular accumulation unit for multilinear modular hash and a pipelined binary modulo unit for modular arithmetic hash. Plentiful experiment results demonstrate the high performance and reliability of our scheme. It can be embedded in most standalone QKD devices conveniently. What's more, it is also a good candidate for a chip-based QKD system.