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The Japan Society of Applied Physics

Demonstration of single flux quantum logic gates by using local magnetic flux bias technique

Shunta Asada, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Jan 28, 2020• 0 citations
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Design and evaluation of single flux quantum circuits by using local magnetic flux bias technique

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Demonstration of an efficient single flux quantum logic circuit by introducing a local magnetic flux biasing

Shunta Asada, Yuki Yamanashi, Nobuyuki Yoshikawa

Abstract We investigated local magnetic flux biasing (LFB) that induces a phase shift in superconductor circuits by locally applying a magnetic field through the superconductor loop with Josephson junctions. The arbitrary phase shift can be achieved using LFB without modifying the circuit fabrication process. To quantitatively evaluate the effects of introducing LFB for practical superconductor circuit applications, we designed a single flux quantum (SFQ) based non-destructive read-out flip-flop with complementary outputs (NDROC) and a delay flip-flop with complementary outputs (DFFC). The circuit area and static power consumption of the NDROC based on LFB architecture (LFB-NDROC) are approximately 67% and 36% of a conventional NDROC, respectively. The measured bias margin of the LFB-NDROC was in the range of 69%–129%. Using LFB, we were able to reduce the circuit area and power consumption for the DFFC by 67% and 83%, respectively. The measured bias margin of the DFFC with LFB was between 115% and 128%. LFB enabled us to implement a 5-to-32 SFQ decoder which comprises NDROC trees with a reduced circuit area of approximately 60% of a conventional decoder. The results obtained in this study can be applied to not just SFQ circuits but other superconductor circuits also, as they improve the area and power efficiency of such circuits.

Superconductor Science and Technology•Mar 25, 2021•2 citations

Design and evaluation of single flux quantum circuits using local flux bias

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We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.

IEEE Transactions on Applied Superconductivity•Mar 1, 2001•0 citations
Abstract We investigated local magnetic flux biasing (LFB) that induces a phase shift in superconductor circuits by locally applying a magnetic field through the superconductor loop with Josephson junctions. The arbitrary phase shift can be achieved using LFB without modifying the circuit fabrication process. To quantitatively evaluate the effects of introducing LFB for practical superconductor circuit applications, we designed a single flux quantum (SFQ) based non-destructive read-out flip-flop with complementary outputs (NDROC) and a delay flip-flop with complementary outputs (DFFC). The circuit area and static power consumption of the NDROC based on LFB architecture (LFB-NDROC) are approximately 67% and 36% of a conventional NDROC, respectively. The measured bias margin of the LFB-NDROC was in the range of 69%–129%. Using LFB, we were able to reduce the circuit area and power consumption for the DFFC by 67% and 83%, respectively. The measured bias margin of the DFFC with LFB was between 115% and 128%. LFB enabled us to implement a 5-to-32 SFQ decoder which comprises NDROC trees with a reduced circuit area of approximately 60% of a conventional decoder. The results obtained in this study can be applied to not just SFQ circuits but other superconductor circuits also, as they improve the area and power efficiency of such circuits.
We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.