Energy-efficient rapid single flux quantum (ERSFQ) circuits are often considered to have two working states including ERSFQ (zero static power dissipation) and RESFQ (resistive energy-efficient SFQ) state. In our previous research, a new working state called MIDSFQ state has been also found in which the biasing JJs cannot return to the non-voltage state after the dynamic process. Both the RESFQ and MIDSFQ states result in extra power dissipation and should be avoided if possible. In this paper, we investigate the characteristics of these three states and explain the working principle of the MIDSFQ state using the hysteresis effect. We obtain an optimization scenario to eliminate the MIDSFQ state and furthermore, a simple but effective method to improve power efficiency of ERSFQ circuits.
Energy-efficient rapid single flux quantum (ERSFQ) circuits are often considered to have two working states including ERSFQ (zero static power dissipation) and RESFQ (resistive energy-efficient SFQ) state. In our previous research, a new working state called MIDSFQ state has been also found in which the biasing JJs cannot return to the non-voltage state after the dynamic process. Both the RESFQ and MIDSFQ states result in extra power dissipation and should be avoided if possible. In this paper, we investigate the characteristics of these three states and explain the working principle of the MIDSFQ state using the hysteresis effect. We obtain an optimization scenario to eliminate the MIDSFQ state and furthermore, a simple but effective method to improve power efficiency of ERSFQ circuits.
Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.
Energy-efficient rapid single flux quantum (ERSFQ) circuits have become a viable alternative for the implementation of superconducting circuits due to a large amount of static power consumption in RSFQ circuits. ERSFQ circuits are built upon the popular RSFQ logic circuits by replacing the power-dissipating resistor bias network with a bias network consisting of active devices. In this paper, a simulation study of ERSFQ biasing scheme is carried out by building simulation test benches for both synchronous and asynchronous ERSFQ circuits. A study is carried out to present the optimum value of biasing inductance, influence of the feeding Josephson transmission line (FJTL) and the effect of its size, the effect of the feeding clock frequency, and the effect of the circuit operating frequency. An innovative clock-choking mechanism using magnetic Josephson junctions is also proposed for the FJTL in the case of no logic circuit activity for a current-recycling circuit block, which would help in eliminating the dynamic power consumed due to the switching of bias junctions in a logic circuit. Simulation results for current recycling ERSFQ circuits are presented along with a strategy for implementing large superconducting circuits.
Abstract As a member of the superconducting integrated circuit family, energy-efficient rapid single flux quantum (ERSFQ) circuit combines low-power consumption with high frequency, showing promise for application in high-energy efficient neuromorphic computing and traditional high-performance computing. Previous studies have demonstrated that there are typically two energy dissipation states in working ERSFQ circuits: energy-efficient SFQ state (E-state) and resistive-biased SFQ state (R-state). These states occur at different biasing current ranges, and the sum of the bias margin of these two states is close to the margin of rapid single flux quantum (RSFQ) circuits of the same design. For ultra-low-power applications, the bias current margin of the R-state must be excluded, leading to a substantially narrower bias margin in ERSFQ circuits than in their RSFQ counterparts. In our previous research, we proposed the feeding pulse method to increase the bias current margin by extending the lower boundary of the E-state through the injection of feeding pulses into the feeding Josephson transmission line (FJTL). In this study, we further investigated the current distribution mechanism in ERSFQ circuits and, based on this, proposed a method of optimizing design of the FJTL to redirect excess current to the FJTL, so as to expand the upper boundary of the E-state’s bias current margin. We tested an ERSFQ 8-bit shift register of the ERSFQ by applying methods proposed in this work together with the feeding pulses method proposed before. The results demonstrated that the bias current margin of the E-state expanded from (94%, 98%) to (56%, 116%), corresponding to a 14-times increase, with both the lower and upper boundary successfully extended. Our research addresses the issue of limited current bias margin in ERSFQ circuits during actual operation, providing a more robust ERSFQ technology for future applications in neural networks and high-performance computing.
Abstract Energy-efficient rapid single flux quantum (ERSFQ) circuits suppress the dominant static power dissipation of Rapid SFQ logic by replacing bias resistors with current-limiting bias Josephson junctions (JJs) and inductors. In practice, however, these JJs introduce power dissipation in the DC bias network due to switching events required to correct data-dependent phase imbalances, with dissipation often comparable to that of dynamic power. This paper presents xeSFQ, a new SFQ logic family that integrates alternating SFQ (xSFQ) encoding with ERSFQ biasing. By enforcing a single pulse per line per logical cycle, xeSFQ maintains uniform phase across the circuit, thereby eliminating bias JJ switching during operation and achieving zero bias network power dissipation. Extensive analog simulations and logic synthesis results, from individual gates to ISCAS and EPFL benchmarks, validate this hypothesis and demonstrate the efficiency and scalability advantages of the proposed approach.
Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeoff between circuit activity, energy efficiency, and bias margins for zero static power dissipation ERSFQ circuits. For ERSFQ, dc power is provided by a Josephson transmission line (JTL) called a “feeding” JTL (FJTL), which acts as a voltage source. As a test case, shift registers and multiplexers were laid out and fabricated in both HYPRES's and MIT-LL's 10-kA/cm2fabrication processes and tested at low (~kHz) and high (~GHz) clock frequencies. The functional bias margins for these circuits increase significantly from +/-4% to over +/-19% when the Josephson junction count in the FJTL was increased to ~30% of total dc bias current of the circuit. Based on our findings, we discuss how to optimize ERSFQ circuits for both energy efficiency and dc bias margins.
We present the design and results of experimental verification methods for ultra-low-power digital circuits based on the recently introduced energy-efficient single flux quantum (eSFQ) logic. Similar to another low-power SFQ logic, ERSFQ, eSFQ circuits make use of superconducting dc bias current dividers and thus avoid static power dissipation. As a result, per-gate power dissipation is reduced by two orders of magnitude as compared to conventional rapid single flux quantum and static power dissipation is zero. The eSFQ circuits are fabricated using the HYPRES standard 4.5 kA/cm2process. We integrate a low-pass analog-to-digital modulator with our eSFQ deserializer to enable testing at high speed. In this paper, we demonstrate the viability and performance metrics of eSFQ circuits through functional and high-speed tests. Specifically, we confirmed correct operation and present measured parameter margins.