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Bulletin of the American Physical Society

Design and fabrication of a surface trap for trapped ion quantum computing

W.-D. Zhao, Yue Jiang, Zhichao Mao, Q.-X. Mei, Zichao Zhou, He Li, Luming Duan

Published May 28, 2019• 0 citations
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Ion trap is a promising approach to realizing scalable quantum computer as it presents high coherence time. Silicon, due to its manufacturability, is being considered as a potential substrate to fabricate complex ion-trap designs towards trap miniaturization and on-chip integration of electronics and optics. However, Si ion traps need proper structural design to reduce the substrate RF loss. In this paper, high-resistivity Si substrate materials has been utilized to fabricate surface electrode ion trap. Its DC and RF properties has been investigated and compared to the ion trap fabricated on sapphire substrate, which is one of the most established substrate material for trap fabrication.
We present the design, fabrication and experimental implementation of surface ion traps with Y-shaped junctions. The traps are designed to minimize the pseudopotential variations in the junction region at the symmetric intersection of three linear segments. We experimentally demonstrate robust linear and junction shuttling with greater than 10 6 round-trip shuttles without ion loss. By minimizing the direct line of sight between trapped ions and dielectric surfaces, negligible day-to-day and trap-to-trap variations are observed. In addition to high-fidelity single-ion shuttling, multiple-ion chains survive splitting, ion-position swapping and recombining routines. The development of two-dimensional trapping structures is an important milestone for ion-trap quantum computing and quantum simulations.