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Resolving the positions of defects in superconducting quantum bits

Alexander Bilmes, A. Megrant, Paul V. Klimov, G. Weiß, John M. Martinis, Alexey Vladimirovich Ustinov, Jürgen Lisenfeld

Published Jan 1, 2020• 43 citations
Publisher

Abstract

Solid-state quantum coherent devices are quickly progressing. Superconducting circuits, for instance, have already been used to demonstrate prototype quantum processors comprising a few tens of quantum bits. This development also revealed that a major part of decoherence and energy loss in such devices originates from a bath of parasitic material defects. However, neither the microscopic structure of defects nor the mechanisms by which they emerge during sample fabrication are understood. Here, we present a technique to obtain information on locations of defects relative to the thin film edge of the qubit circuit. Resonance frequencies of defects are tuned by exposing the qubit sample to electric fields generated by electrodes surrounding the chip. By determining the defect’s coupling strength to each electrode and comparing it to a simulation of the field distribution, we obtain the probability at which location and at which interface the defect resides. This method is applicable to already existing samples of various qubit types, without further on-chip design changes. It provides a valuable tool for improving the material quality and nano-fabrication procedures towards more coherent quantum circuits.

DOI
10.5445/ir/1000117700

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Solid-state quantum coherent devices are quickly progressing. Superconducting circuits, for instance, have already been used to demonstrate prototype quantum processors comprising a few tens of quantum bits. This development also revealed that a major part of decoherence and energy loss in such devices originates from a bath of parasitic material defects. However, neither the microscopic structure of defects nor the mechanisms by which they emerge during sample fabrication are understood. Here, we present a technique to obtain information on locations of defects relative to the thin film edge of the qubit circuit. Resonance frequencies of defects are tuned by exposing the qubit sample to electric fields generated by electrodes surrounding the chip. By determining the defect’s coupling strength to each electrode and comparing it to a simulation of the field distribution, we obtain the probability at which location and at which interface the defect resides. This method is applicable to already existing samples of various qubit types, without further on-chip design changes. It provides a valuable tool for improving the material quality and nano-fabrication procedures towards more coherent quantum circuits.
Solid-state quantum coherent devices are quickly progressing. Superconducting circuits, for instance, have already been used to demonstrate prototype quantum processors comprising a few tens of quantum bits. This development also revealed that a major part of decoherence and energy loss in such devices originates from a bath of parasitic material defects. However, neither the microscopic structure of defects nor the mechanisms by which they emerge during sample fabrication are understood. Here, we present a technique to obtain information on locations of defects relative to the thin film edge of the qubit circuit. Resonance frequencies of defects are tuned by exposing the qubit sample to electric fields generated by electrodes surrounding the chip. By determining the defect's coupling strength to each electrode and comparing it to a simulation of the field distribution, we obtain the probability at which location and at which interface the defect resides. This method is applicable to already existing samples of various qubit types, without further on-chip design changes. It provides a valuable tool for improving the material quality and nano-fabrication procedures towards more coherent quantum circuits.
Abstract Superconducting integrated circuits have demonstrated a tremendous potential to realize integrated quantum computing processors. However, the downside of the solid-state approach is that superconducting qubits suffer strongly from energy dissipation and environmental fluctuations caused by atomic-scale defects in device materials. Further progress towards upscaled quantum processors will require improvements in device fabrication techniques, which need to be guided by novel analysis methods to understand and prevent mechanisms of defect formation. Here, we present a technique to analyse individual defects in superconducting qubits by tuning them with applied electric fields. This provides a spectroscopy method to extract the defects’ energy distribution, electric dipole moments, and coherence times. Moreover, it enables one to distinguish defects residing in Josephson junction tunnel barriers from those at circuit interfaces. We find that defects at circuit interfaces are responsible for about 60% of the dielectric loss in the investigated transmon qubit sample. About 40% of all detected defects are contained in the tunnel barriers of the large-area parasitic Josephson junctions that occur collaterally in shadow evaporation, and only ≈\approx≈ ≈ 3% are identified as strongly coupled defects, which presumably reside in the small-area qubit tunnel junctions. The demonstrated technique provides a valuable tool to assess the decoherence sources related to circuit interfaces and to tunnel junctions that is readily applicable to standard qubit samples.
The coherence of superconducting quantum computers is severely limited by material defects that create parasitic two-level-systems (TLS). Progress is complicated by lacking understanding how TLS are created and in which parts of a qubit circuit they are most detrimental. Here, we present a method to determine the individual positions of TLS at the surface of a transmon qubit. We employ a set of onchip gate electrodes near the qubit to generate local DC electric fields that are used to tune the TLS’ resonance frequencies. The TLS position is inferred from the strengths at which TLS couple to different electrodes and comparing them to electric field simulations. We found that the majority of detectable surface-TLS was residing on the leads of the qubit’s Josephson junction, despite the dominant contribution of its coplanar capacitor to electric field energy and surface area. This indicates that the TLS density is significantly enhanced near shadow-evaporated electrodes fabricated by lift-off techniques. Our method is useful to identify critical circuit regions where TLS contribute most to decoherence, and can guide improvements in qubit design and fabrication methods.
The coherence of superconducting quantum computers is severely limited by material defects that create parasitic two-level-systems (TLS). Progress is complicated by lacking understanding how TLS are created and in which parts of a qubit circuit they are most detrimental. Here, we present a method to determine the individual positions of TLS at the surface of a transmon qubit. We employ a set of on-chip gate electrodes near the qubit to generate local DC electric fields that are used to tune the TLS' resonance frequencies. The TLS position is inferred from the strengths at which TLS couple to different electrodes and comparing them to electric field simulations. We found that the majority of detectable surface-TLS was residing on the leads of the qubit's Josephson junction, despite the dominant contribution of its coplanar capacitor to electric field energy and surface area. This indicates that the TLS density is significantly enhanced near shadow-evaporated electrodes fabricated by lift-off techniques. Our method is useful to identify critical circuit regions where TLS contribute most to decoherence, and can guide improvements in qubit design and fabrication methods.
Abstract The coherence of superconducting quantum computers is severely limited by material defects that create parasitic two-level-systems (TLS). Progress is complicated by lacking understanding how TLS are created and in which parts of a qubit circuit they are most detrimental. Here, we present a method to determine the individual positions of TLS at the surface of a transmon qubit. We employ a set of on-chip gate electrodes near the qubit to generate local DC electric fields that are used to tune the TLS’ resonance frequencies. The TLS position is inferred from the strengths at which TLS couple to different electrodes and comparing them to electric field simulations. We found that the majority of detectable surface-TLS was residing on the leads of the qubit’s Josephson junction, despite the dominant contribution of its coplanar capacitor to electric field energy and surface area. This indicates that the TLS density is significantly enhanced near shadow-evaporated electrodes fabricated by lift-off techniques. Our method is useful to identify critical circuit regions where TLS contribute most to decoherence, and can guide improvements in qubit design and fabrication methods.