Quantum modular multiplication circuit is one of the basic quantum computation circuits which are basic functions in quantum algorithms. However, since quantum-quantum modular multipliers require a high cost reversible modular inversion routine for modular multiplication, researchers have been unable to propose a feasible quantum-quantum modular multiplier. In this paper, we proposed efficient quantum-classical modular multipliers and the first quantum-quantum modular multipliers that do not require a reduction stage by transforming the partial product used in multiplication utilizing bit-shift operation. Then, we calculated quantum resource complexity and analyzed it compared to other quantum modular multipliers and utilized ETRI (Electronics and Telecommunications Research Institute) Qcrypton to analyze quantum resource complexity in the practical quantum computing situation. The proposed quantum modular multipliers show an improvement of 50% in terms of gates and circuit depth compared to the most recently proposed high-performance quantum modular multipliers.
Quantum modular multiplication circuit is one of the basic quantum computation circuits which are basic functions in quantum algorithms. However, since quantum-quantum modular multipliers require a high cost reversible modular inversion routine for modular multiplication, researchers have been unable to propose a feasible quantum-quantum modular multiplier. In this paper, we proposed efficient quantum-classical modular multipliers and the first quantum-quantum modular multipliers that do not require a reduction stage by transforming the partial product used in multiplication utilizing bit-shift operation. Then, we calculated quantum resource complexity and analyzed it compared to other quantum modular multipliers and utilized ETRI (Electronics and Telecommunications Research Institute) Qcrypton to analyze quantum resource complexity in the practical quantum computing situation. The proposed quantum modular multipliers show an improvement of 50% in terms of gates and circuit depth compared to the most recently proposed high-performance quantum modular multipliers.
Due to the reversibility constraints of quantum circuits, the development of modular operations in quantum modular multiplication has been significantly limited. In this work, we propose an optimized modular operation scheme based on Barrett reduction and implement quantum circuits for three versions of Barrett reduction, including our optimized approach. The proposed quantum modular operation circuit can be integrated with quantum-quantum and quantum-classical multiplication circuits. Additionally, we analyze the quantum resource requirements of the proposed circuit and compare the results across the three versions. Our optimized folding Barrett reduction scheme demonstrates superior performance. Furthermore, general quantum modular reduction relies on recursive subtractors and controlled adders to avoid division operation, resulting in a T-depth of approximately [Formula: see text], where n is the bit length of the modulus. In contrast, our approach achieves a T-depth of only [Formula: see text] by utilizing the Barrett reduction.
Quantum modular multipliers are a promising development in the field of quantum computing that aim to perform modular multiplication faster and more efficiently than classical algorithms. This is achieved by encoding the numbers being multiplied into quantum bits (qubits) and using quantum gates to manipulate them in a way that represents the calculation. Since quantum physics principles like superposition and entanglement dramatically speed up processing compared to conventional computing, many calculations may be run simultaneously. Quantum modular multipliers have the potential to have a significant impact in a range of fields, including cryptography and beyond, since they offer a faster and more efficient way to do modular multiplications. Several fields, including simulation, optimization, and cryptography, can benefit from the use of quantum computing.One of the crucial operations in many of these applications is modular multiplication, a sort of multiplication that requires obtaining the remainder of the product of two numbers when divided by a third number. In this paper, we provide a novel modular multiplication method based on a quantum algorithm. To examine its complexity and compare it to that of current adders, we employ a novel form of adder that is intended to not retain the final carry. This adder's decrease percentage in terms of gates and depth is roughly 70%. Our method takes advantage of the special qualities of qubits to complete the computation significantly more quickly than conventional algorithms. It is based on the fundamental ideas of quantum physics, such as superposition and entanglement.
We present a novel set of reversible modular multipliers applicable to quantum computing, derived from three classical techniques: 1) traditional integer division, 2) Montgomery residue arithmetic, and 3) Barrett reduction. Each multiplier computes an exact result for all binary input values, while maintaining the asymptotic resource complexity of a single (non-modular) integer multiplier. We additionally conduct an empirical resource analysis of our designs in order to determine the total gate count and circuit depth of each fully constructed circuit, with inputs as large as 2048 bits. Our comparative analysis considers both circuit implementations which allow for arbitrary (controlled) rotation gates, as well as those restricted to a typical fault-tolerant gate set.
In this study, we propose an efficient quantum multiplication approach based on a QFT-assisted parallelized addition scheme. The multiplication stage is implemented using a structure composed entirely of Toffoli gates, which generate partial products. In the second stage, these partial results are accumulated using a QFT-based adder. Unlike conventional QFT-based arithmetic circuits, the proposed design eliminates the repeated application of QFT and inverse QFT (IQFT) operations during intermediate summation processes. This leads to a significant reduction in the total gate count and circuit complexity, enabling a more resource-efficient implementation. To demonstrate the feasibility of the proposed approach, a quantum circuit that performs the multiplication of two 3-bit numbers is designed. The circuit is tested and validated using IBM quantum simulators. The results indicate that the proposed method provides a more efficient alternative to traditional quantum multiplication techniques in terms of gate cost and circuit depth.
Reversible logic is one of the stepping stones in low power circuit design. Due to low power consumption and minimum bit loss features, future quantum computing devices are estimated to be reversible. Compared to addition, multiplication is a step further in the ladder of abstraction. It is the manifestation of a pattern generation system capable of representing 3-D patterns and transforming them by rotation, projection, reflection etc. The use of reversible logic in this field can reduce the wastage of energy, power and improve many factors. In this paper, an efficient multiplication algorithm has been proposed which is a modification of conventional shift-and-add multiplication method. Implementing proposed algorithm two reversible multiplier circuit has been proposed. For producing partial product, Peres gate has been used for the first design and Toffoli gate for the second design. Both of the circuits use Peres gate as Half-Adder and HNG gate as Full-Adder for addition of partial products. The first design is improved radically in terms of quantum cost, delay and the second design is notably improved in terms of transistor count and hardware complexity compared to the existing best known multipliers.
We present a quantum algorithm for multiplying two n-bit integers with overall circuit depth and T-depth both bounded by O(logn), while using O(n2) gates and ancillary qubits. Our construction generates partial products via indicator-controlled copying and adds them using a tree of reversible 3-to-2 adders followed by one quantum carry-lookahead adder. Building on the carry-save adders of Kim et al., we combine full input fanout, workspace reuse, and phase-corrected gate implementations to reduce T-depth. We provide explicit circuit constructions, proofs of correctness, and concrete closed-form resource bounds.