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IEEE Symposium on Computers and Communications (ISCC)

A High-Throughput LDPC Decoder Based on GPUs for 5G New Radio

Rongchun Li, Xin Zhou, Hengyue Pan, Huayou Su, Yong Dou

Published Jul 1, 2020• 11 citations
Publisher

Abstract

In this paper, we propose a GPU-based QC-LDPC decoder for 5G New Radio(NR). Different from existing LDPC decoders based on GPUs, our decoder achieves high throughput when decoding LDPC codes with high code rates. Moreover, we implement the shortening and puncturing techniques which are exploited by 5G NR. The decoding algorithm Min-Sum approximation algorithm(MSA) is optimized to implement efficient parallel decoding on the GPU. In order to save the on-chip and the off-chip bandwidth, we propose the two-level quantization scheme and implement data packing on the GPU. We also analyse the optimum thread assignment for different code rates based on our implementation. By using the optimum settings on the GPU, the decoding throughput achieves 1.38 Gbps in the case of (2080, 1760), r=5/6 on Nvidia RTX 2080Ti.

DOI
10.1109/iscc50000.2020.9219558

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•Jan 1, 2022•0 citations
In this paper, we propose a GPU-based QC-LDPC decoder for 5G New Radio(NR). Different from existing LDPC decoders based on GPUs, our decoder achieves high throughput when decoding LDPC codes with high code rates. Moreover, we implement the shortening and puncturing techniques which are exploited by 5G NR. The decoding algorithm Min-Sum approximation algorithm(MSA) is optimized to implement efficient parallel decoding on the GPU. In order to save the on-chip and the off-chip bandwidth, we propose the two-level quantization scheme and implement data packing on the GPU. We also analyse the optimum thread assignment for different code rates based on our implementation. By using the optimum settings on the GPU, the decoding throughput achieves 1.38 Gbps in the case of (2080, 1760), r=5/6 on Nvidia RTX 2080Ti.
In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.
5G technology new radios (5G NR) require high-speed decoders that operate on highly irregular low-density parity-check (LDPC) codes.LDPC decoders have gained significant attention due to their excellent error correction performance.This study evaluates on different algorithms and scheduling techniques used for LDPC decoders.The analysis highlights that Min-Sum-based approaches can reduce the computational complexity compared to the basic sum-product algorithm, while the normalized and extended Min-Sum algorithms provide a better trade-off owing to their accurate value assumptions.Furthermore, different scheduling methods are implied for MS to improve speed and reduce latency.This study provides a comparative analysis of the algorithms and architectures that yield high throughputs without compromising performance efficiency.The LNMS algorithm with a data-level rescheduling technique resolves data dependency issues.This resolves the complexity of CN and VN and improves the throughput, making it suitable for 5G NR applications.The decoded throughput achieved with this scheduling is 7.0 Gbps.This throughput is achieved by maintaining the standard parameters and worst case parameters, such as four/eight iterations, BG1, and a code rate of 0.8/0.5.The evaluated architectures are implemented on Field Programmable Gate Array (FPGA) devices.This study aids in selecting the optimal architecture and scheduling techniques for LDPC decoders by considering various performance standards to deploy wireless networks in 5G and beyond.
This thesis presents a study on implementing a low-density parity-check (LDPC) decoder on a graphics processing unit (GPU) for 5G New Radio (NR). The proposed modifications include distributed execution configuration, compressed parity-check matrices (PCM) and message passing matrices to save memory space and applying the optimal iteration limit to the decoder. The performance of the LDPC decoder is evaluated using various testing cases with different algorithms, code rates and transport block sizes. The results show that the proposed decoder has more than 5× decoding speedup improvement on the short codes and more than 20× decoding speedup improvement on the long codes, while maintaining the error-correction performance. The optimal iteration limit is found to depend on the specific code rate and transport block size. The layered scheduling is a viable option on short codes over noisy channels.
This paper presents a high-throughput decoding method for quasi-cyclic low-density parity-check (QC-LDPC) codes, optimized for both CPU and GPU-based Software-Defined Radios (SDRs). The approach leverages a SIMD data alignment architecture that minimizes cache misses and is designed to take full advantage of modern CPUs and GPUs with rich registers and caches. An innovative decoding algorithm is introduced, exploiting the SIMD capabilities of contemporary CPUs to enhance parallelism, while optimizing memory access patterns to align SIMD operations and minimize branching and cache misses on AMD EPYC CPUs (2xEPYC-9754). This results in significant throughput improvements. The method is further extended to GPUs, utilizing their large-scale parallelism through efficient use of registers and local memory. To maximize performance, a memory-efficient check node decoding strategy is employed, ensuring that operations fit within the cache of the Streaming Multiprocessors (SM) to reduce memory access overhead. Simulation results demonstrate the effectiveness of this approach: the CPU-based 8-iteration layered min-sum decoder with early termination achieves coded bit throughputs of up to 72.9 Gbps for 16200-bit codes and 50.9 Gbps for 64800-bit DVB-S2 QC-LDPC codes. On GPUs, the decoder reaches 132 Gbps for short 802.11n Wi-Fi 1944-bit codes and 22.3 Gbps for 5G Base Graph 1 26112-bit codes on an NVIDIA RTX 4090. For 6G prototype QC-LDPC codes, the proposed 3-layer design achieves up to 76 Gbps for 1920-bit codes, with surpassing 104 Gbps on the NVIDIA RTX 5090. Compared to the open-source AFF3CT CPU framework, the proposed method offers 5 to 12 times higher throughput across various code lengths. Even when AFF3CT is optimized with MIPP intrinsics, the new decoder provides 3.2 to 5.7 times better throughput. The GPU implementation delivers up to 120 times the speed of previously published results and offers 13 to 40 times improvement over older GPUs like the GTX 1080 Ti and Titan X, scaling effectively with modern GPUs like the RTX 4090. This approach establishes new performance benchmarks for QC-LDPC decoding, positioning it as an ideal solution for next-generation 5G/6G wireless and satellite communications.
In this paper, we present a high throughput and low latency LDPC (low-density parity-check) decoder implementation on GPUs (graphics processing units). The existing GPU-based LDPC decoder implementations suffer from low throughput and long latency, which prevent them from being used in practical SDR (software-defined radio) systems. To overcome this problem, we present optimization techniques for a parallel LDPC decoder including algorithm optimization, fully coalesced memory access, asynchronous data transfer and multi-stream concurrent kernel execution for modern GPU architectures. Experimental results demonstrate that the proposed LDPC decoder achieves 316 Mbps (at 10 iterations) peak throughput on a single GPU. The decoding latency, which is much lower than that of the state of the art, varies from 0.207 ms to 1.266 ms for different throughput requirements from 62.5 Mbps to 304.16 Mbps. When using four GPUs concurrently, we achieve an aggregate peak throughput of 1.25 Gbps (at 10 iterations).
Low-Density Parity-Check (LDPC) codes are linear error-correcting codes used to establish reliable communication between units on a noisy transmission channel in mobile telecommunications. LDPC algorithms detect and recover altered or corrupted message bits using sparse parity-check matrices in order to decipher messages correctly. LDPC codes have been shown to be fitting coding schemes for the fifth generation (5G) New Radio (NR), according to the third generation partnership project (3GPP). TietoEvry, a consultant in telecom, has discovered that optimizations of LDPC decoding algorithms can be achieved/obtained with the use of a parallel computing platform called Compute Unified Device Architecture (CUDA), developed by NVIDIA. This platform utilizes the capabilities of a graphics processing unit (GPU) rather than a central processing unit (CPU), which in turn provides parallel computing. An optimized version of an LDPC decoding algorithm, the Min-Sum Algorithm (MSA), is implemented in CUDA and in C++ for comparison in terms of CPU execution time, to explore the capabilities that CUDA offers. The testing is done with a set of 12 sparse parity-check matrices and input-channel messages with different sizes. As a result, the CUDA implementation executes approximately 55% faster than a standard, unoptimized C++ implementation.