IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Information Storage Bit-Flipping Decoder for LDPC Codes

Hangxuan Cui, Jun Ting Lin, Zhongfeng Wang

Published Sep 17, 2020• 18 citations

Abstract

Tabu-list random-penalty gradient descent bit-flipping (TRGDBF) decoder is the state-of-the-art hard-decision low-density parity-check (LDPC) decoder in terms of error-correction performance on binary symmetric channel (BSC). However, the TRGDBF decoder suffers from a long critical path caused by the global maximum-finding operation, limiting the achievable throughput. This brief proposes an information storage bit-flipping (ISBF) decoder to solve this problem. Different from the existing bit-flipping (BF) decoders which adopt serial decoding manner, in the ISBF decoder, by storing the previous decoding information, the global maximum-finding operation can be executed in parallel to other decoding operations, significantly shortening the critical path. Moreover, a nonuniform flipping rule is incorporated to achieve a better decoding performance. We also present an efficient architecture to implement the ISBF decoder. The design example demonstrates that compared to other hard-decision BF decoders, the ISBF decoder could provide both the best decoding performance and throughput on BSC.

DOI: 10.1109/tvlsi.2020.3009270

Related papers

An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes

Hangxuan Cui, Jun Ting Lin, Zhongfeng Wang

Low-complexity and high-performance low-density parity-check (LDPC) decoders are highly demanded in various modern communication and storage systems. In this paper, a novel hard-decision decoding algorithm, called tabu-list random-penalty gradient descent bit-flipping (TRGDBF) algorithm, is proposed. Compared to the state-of-the-art hard-decision algorithms, the TRGDBF algorithm has much better error-correction performance due to several algorithmic improvements. First, a random-penalty term is introduced to the inversion function to help the decoder escape from trapping sets, which are the main causes of the error-floor phenomenon. Second, a tabu-list is employed to improve the decoding efficiency. Numerical results show that the TRGDBF algorithm can achieve up to two orders of magnitude better error-correction performance than the probabilistic gradient descent bit-flipping (PGDBF) algorithm and reduce the average iteration count by about 15%. In addition, a well-optimized hardware architecture is developed to implement the TRGDBF algorithm. Algorithmic transformation and architecture optimization are well explored to reduce the hardware complexity and latency. Synthesis results show that the TRGDBF decoder can work at a higher frequency and offer a larger throughput than the PGDBF decoder.

IEEE Transactions on Circuits and Systems I Regular PapersApr 17, 201930 citations

Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes

Keyue Deng, Hangxuan Cui, Jun Ting Lin +1 more

Tabu-list random-penalty gradient descent bit-flipping (TRGDBF) is a hard-decision algorithm for decoding low-density parity-check (LDPC) codes, which offers a significant improvement in error correction. However, compared to the current gradient descent bit-flipping (GDBF) variants, it converges slower and has no obvious performance advantage unless enough iterations are allowed. To accelerate the convergence speed, this paper presents a counter random GDBF (CRGDBF) algorithm in which a bit is forbidden to flip in the next iteration after being flipped several times. Incorporating the random operation, the forbidden-mechanism shows a dynamic property, facilitating the decoder more efficiently to break trapping sets. Simulation results show that the CRGDBF can achieve up to 5 times better decoding performance than the TRGDBF algorithm within finite iterations. Additionally, an architecture is presented for implementing the CRGDBF algorithm, demonstrating it only brings limited hardware overhead compared to the TRGDBF.

IEEE Computer Society Annual Symposium on VLSIJul 1, 20216 citations

A New Probabilistic Gradient Descent Bit Flipping Decoder for LDPC Codes

Hangxuan Cui, Jun Ting Lin, Suwen Song +1 more

Probabilistic gradient descent bit-flipping (PGDBF) is the state-of-the-art hard-decision algorithm for decoding low-density parity-check (LDPC) codes on binary symmetric channel (BSC). However, there still exists a considerable performance gap between the PGDBF algorithm and soft-decision algorithms, especially in the error-floor region. To bridge this performance gap, a tabu-list aided PGDBF (T-PGDBF) algorithm is proposed in this paper. In the T-PGDBF algorithm, a tabu-list is employed to help the decoding escape from trapping sets, which is the main cause of the error-floor phenomenon. The bits which are flipped in the current iteration will be added to the tabu-list to prevent them being flipped in the next iteration. Simulation results show that the T-PGDBF algorithm offers a significant performance gain when compared to the PGDBF algorithm, which can reach that of soft-decision algorithms. We also present the hardware architecture to implement the T-PGDBF algorithm. Synthesis results show that the improved performance offered by the T-PGDBF algorithm can be obtained with a small hardware overhead.

IEEE International Symposium on Circuits and Systems proceedingsMay 1, 20198 citations

A novel high-throughput, low-complexity bit-flipping decoder for LDPC codes

Khoa Le, Fakhreddine Ghaffari, David Declercq +2 more

This paper presents a new high-throughput, low-complexity Bit Flipping (BF) decoder for Low-Density Parity-Check (LDPC) codes on the Binary Symmetric Channel (BSC), called Probabilistic Parallel Bit Flipping (PPBF). The advantage of PPBF comes from the fact that, no global operation is required during the decoding process and from that, all of the computations could be parallelized and localized at the computing units. Also in PPBF, the probabilistic feature in flipping the Variable Node (VN) is incorporated for all satisfaction level of its CN neighbors. This type of probabilistic incorporation makes PPBF more dynamic to correct some error patterns which are unsolvable by other BF decoders. PPBF offers a faster decoding process with an equivalent error correction performance to the Probabilistic Gradient Descent Bit Flipping (PGDBF) decoder, which is better than all so-far introduced BF decoders in BSC channel. A hardware implementation architecture of PPBF is also presented in this paper with detailed circuits for the probabilistic signal generator and processing units. The implementation of PPBF on FPGA confirms that, the PPBF complexity is much lower than that of the PGDBF and even lower than the one of the deterministic Gradient Descent Bit Flipping (GDBF) decoder. The good decoding performance along with the high throughput and low complexity lead PPBF decoder to become a brilliant candidate for the next generation of communication and storage standards.

International Conference on Advanced Technologies for CommunicationsOct 1, 201714 citations

Multiple Flipping Strategy LISBF for LDPC Codes

Yishan Sun, Pingyang Huang, Yichun Zhang +1 more

The performance and complexity of low-density parity-check (LDPC) decoders have strict requirements since they are widely demanded in both communication and storage systems. Information storage bit flipping (ISBF) decoder and layered ISBF (LISBF) decoder demonstrate excellent decoding performance and throughput in which the global maximumfinding operation can be calculated in parallel to other decoding operations. However, their error-correction performance is not satisfactory. In this paper, we consider a variety of optimizations based on LISBF and propose a new algorithm named multiple flipping strategy LISBF (MLISBF). First, a high probability is adopted to flip those bits with high energy values. Second, strict flipping with a lower threshold is triggered when the syndrome weight is negligible. Then, we introduce perturbation flipping at specific iterations to help the decoder overcome trapping sets. We designed an efficient hardware implementation which realizes the layered calculation for BF decoders and reduces hardware resources for the MLISBF algorithm.

World Conference on Computing and Communication Technologies (WCCCT)Jan 6, 20231 citation

Design and Implementation of Hard-Decision LDPC Decoder

Yi Dong, Huimin Du, Shengfei Bai +3 more

Hard-decision LDPC decoders are widely used in communication and storage systems due to their simple circuits. However, existing hard decision LDPC decoding circuits lead to slow decoding convergence due to flipping according to the maximum energy value, reducing decoding performance. This paper proposes the Dual-Energy Probabilistic Gradient Descent Bit-Flipping (DPGDBF) hard-decision algorithm. If the energy value of the variable node reaches the threshold, all nodes with the threshold energy will be flipped, and the node with the sub-maximum threshold energy will be flipped with a certain probability. otherwise, only all variable nodes with the maximum energy value are flipped. The simulation results show that, in a limited iterative range, compared with Tabu-list Random-Penalty Gradient Descent Bit-Flipping (TRGDBF), for (2048, 1024) codes, the average number of decoding iterations of the algorithm is reduced by 12%, and the decoding performance is improved to a certain extent; for (9216,7680) codes, the average number of decoding iterations of the DPGDBF algorithm is reduced by 18%, and the decoding performance is improved by 4 times. In addition, this paper proposes a hardware implementation of the DPGDBF algorithm for (2048, 1024) codes, with a maximum clock frequency of 305.53MHz and a through-put of 19.52Gbps.

International Conference on Integrated Circuits and Microsystems (ICICM)Oct 28, 20220 citations