Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Quantum Information Processing

Qubits’ mapping and routing for NISQ on variability of quantum gates

Ze‐Tong Li, Fan‐Xu Meng, Zaichen Zhang, Xutao Yu

Published Oct 1, 2020• 12 citations
Publisher
DOI
10.1007/s11128-020-02873-5

Related papers

TETRIS-Q: Tiling-based Effective Transient-fault Reduction and Parallelism Optimizations for Quantum Circuit Mapping

Rowan Brad Quni-Gudzinas

Quantum circuit mapping on Noisy Intermediate-Scale Quantum (NISQ) devices must satisfy physical connectivity constraints while minimizing both SWAP overhead and exposure to transient faults like decoherence. Existing compilers typically optimize qubit routing and noise-aware placement independently, failing to jointly exploit spatial structure to reduce both SWAP depth and idle-time-induced decoherence. We introduce TETRIS-Q, a mapping framework that partitions the physical qubit topology into local rectangular tiles. This tiling abstraction enables a unified strategy: tile-local mapping minimizes idle qubit lifetimes, while cross-tile parallel scheduling maximizes concurrent two-qubit gate execution. By treating transient-fault probability as a function of idle duration and gate ordering, rather than just circuit depth, TETRIS-Q jointly penalizes SWAP count and cumulative idle time. On grid-heavy architectures, we project a 10–30% reduction in SWAP count [to verify] and measurable fidelity improvements over routing-only baselines [to verify]. This approach demonstrates that spatial tiling offers a robust paradigm for high-fidelity NISQ compilation. ## 1. Introduction Compiling quantum algorithms for Noisy Intermediate-Scale Quantum (NISQ) hardware requires mapping logical qubits onto physical qubits with limited connectivity. To execute gates between non-adjacent physical qubits, compilers insert SWAP gates—operations that exchange qubit states—to route interacting qubits into adjacency. While SWAP gates introduce additional circuit depth and gate errors, they also indirectly increase exposure to transient faults (decoherence and relaxation, characterized by T1 and T2 timescales) by extending the duration that idle qubits wait for dependent operations. Existing quantum compilers generally treat routing minimization and noise-aware placement as separate optimization passes. However, this independent optimization misses opportunities to exploit the spatial locali

•Sep 8, 2026•0 citations

Proposal of Quantum Circuits and Qubit Mapping Optimization

賢太 海老澤, 1477, Kenta Ebisawa

•Oct 1, 2025•0 citations

Mapping of quantum circuits onto NISQ superconducting processors

Lingling Lao, Daniel Manzano, Hans van Someren +2 more

•Aug 12, 2019•18 citations

Transverse relaxation time–aware qubit-mapping algorithm for noisy intermediate-scale quantum devices

Anonymous, Pascal J. Elahi, Ugo Varetto +3 more

Noisy intermediate-scale quantum (NISQ) devices impose dual challenges on quantum circuit execution: limited qubit connectivity requires extensive SWAP-gate routing, while time-dependent decoherence progressively degrades quantum information. Existing qubit-mapping algorithms optimize for hardware topology and static calibration metrics but systematically neglect transverse relaxation dynamics (T_2), creating a fundamental gap between compiler decisions and evolving noise characteristics. We present transverse relaxation time–aware qubit-mapping (TRAM), a coherence-guided compilation framework that elevates decoherence mitigation to a primary optimization objective. TRAM integrates calibration-informed community detection to construct noise-resilient qubit partitions, generates time-weighted initial mappings that anticipate coherence decay, and dynamically schedules SWAP operations to minimize cumulative error accumulation. Evaluated on Qiskit-based simulators with realistic noise models, TRAM outperforms SABRE by 3.29% in fidelity, reduces gate count by 11.47%, and shortens circuit depth by 12.29%, establishing coherence-aware optimization as essential for practical quantum compilation in the NISQ era.

Physical Review Applied•Aug 17, 2026•0 citations

Hierarchical Parallel Computing for Optimal Qubit Mapping in NISQ Systems

Jean-Philippe Valois, Guillaume Helbecque, Nouredine Melab

Lecture notes in computer science•Aug 14, 2026•0 citations

An Ising-based Model for Qubit Mapping

Hayato Ushijima‐Mwesigwa, Xiaoyuan Liu

A crucial step in compiling a quantum algorithm involves addressing a layout problem to meet the device’s layout constraints. The Qubit Mapping and Routing (QMR) problem aims to minimize the number of SWAP gates added to the circuit to fulfill NISQ hardware’s connectivity constraints. Although this problem is NP-hard, finding solutions quickly is vital as it is part of the compilation process.

International Conference for High Performance Computing, Networking, Storage and Analysis (SC)•Nov 10, 2023•0 citations
Quantum circuit mapping on Noisy Intermediate-Scale Quantum (NISQ) devices must satisfy physical connectivity constraints while minimizing both SWAP overhead and exposure to transient faults like decoherence. Existing compilers typically optimize qubit routing and noise-aware placement independently, failing to jointly exploit spatial structure to reduce both SWAP depth and idle-time-induced decoherence. We introduce TETRIS-Q, a mapping framework that partitions the physical qubit topology into local rectangular tiles. This tiling abstraction enables a unified strategy: tile-local mapping minimizes idle qubit lifetimes, while cross-tile parallel scheduling maximizes concurrent two-qubit gate execution. By treating transient-fault probability as a function of idle duration and gate ordering, rather than just circuit depth, TETRIS-Q jointly penalizes SWAP count and cumulative idle time. On grid-heavy architectures, we project a 10–30% reduction in SWAP count [to verify] and measurable fidelity improvements over routing-only baselines [to verify]. This approach demonstrates that spatial tiling offers a robust paradigm for high-fidelity NISQ compilation. ## 1. Introduction Compiling quantum algorithms for Noisy Intermediate-Scale Quantum (NISQ) hardware requires mapping logical qubits onto physical qubits with limited connectivity. To execute gates between non-adjacent physical qubits, compilers insert SWAP gates—operations that exchange qubit states—to route interacting qubits into adjacency. While SWAP gates introduce additional circuit depth and gate errors, they also indirectly increase exposure to transient faults (decoherence and relaxation, characterized by T1 and T2 timescales) by extending the duration that idle qubits wait for dependent operations. Existing quantum compilers generally treat routing minimization and noise-aware placement as separate optimization passes. However, this independent optimization misses opportunities to exploit the spatial locali
Noisy intermediate-scale quantum (NISQ) devices impose dual challenges on quantum circuit execution: limited qubit connectivity requires extensive SWAP-gate routing, while time-dependent decoherence progressively degrades quantum information. Existing qubit-mapping algorithms optimize for hardware topology and static calibration metrics but systematically neglect transverse relaxation dynamics (T_2), creating a fundamental gap between compiler decisions and evolving noise characteristics. We present transverse relaxation time–aware qubit-mapping (TRAM), a coherence-guided compilation framework that elevates decoherence mitigation to a primary optimization objective. TRAM integrates calibration-informed community detection to construct noise-resilient qubit partitions, generates time-weighted initial mappings that anticipate coherence decay, and dynamically schedules SWAP operations to minimize cumulative error accumulation. Evaluated on Qiskit-based simulators with realistic noise models, TRAM outperforms SABRE by 3.29% in fidelity, reduces gate count by 11.47%, and shortens circuit depth by 12.29%, establishing coherence-aware optimization as essential for practical quantum compilation in the NISQ era.