A hardware approach for the quantum computing modeling was considered. A common mathematical model of the quantum computer was described; a methodic of mathematical modeling of the quantum computing was shown. During the mathematical methodic description the most resource-intensive parts of the model are allocated. Considered questions connected with data parallelizing with a hardware accelerator, which is used for quantum computer modeling. A common scheme of the accelerator’s work algorithm was shown. Suggested more compact data format for accelerator implementation, that will reduce time costs spent by elementary arithmetic operations. Proposed the use of the optimization algorithm for data minimization during the calculations in the phase of transforming model of quantum register with quantum gates in quantum computer simulators. Shown results of optimization algorithm execution and compared results with classic mathematical approach.
A hardware approach for the quantum computing modeling was considered. A common mathematical model of the quantum computer was described; a methodic of mathematical modeling of the quantum computing was shown. During the mathematical methodic description the most resource-intensive parts of the model are allocated. Considered questions connected with data parallelizing with a hardware accelerator, which is used for quantum computer modeling. A common scheme of the accelerator’s work algorithm was shown. Suggested more compact data format for accelerator implementation, that will reduce time costs spent by elementary arithmetic operations. Proposed the use of the optimization algorithm for data minimization during the calculations in the phase of transforming model of quantum register with quantum gates in quantum computer simulators. Shown results of optimization algorithm execution and compared results with classic mathematical approach.
This article discusses the principles of quantum computing simulation using hardware approach. We describe a general mathematical model of a quantum computer; we show the method of mathematical modeling of quantum computation with optimization and a scheme of a hardware processing core in a quantum computing accelerator. The article gives a method of assessment of increasing productivity in the simulation of quantum computations using computing hardware core. The problems associated with the parallelization of computations on a hardware accelerator, simulating quantum computing were analyzed. The work lists the results of comparison of software and hardware simulation, as well as the dependence of the temporal evaluation of the number of qubits and parallel ALU in the computer-hardware accelerator
In the past few decades, there has been an acute problem of creating a quantum computer that uses quantum mechanical effects such as quantum parallelism and quantum entanglement for computations. Using these mechanisms, the quantum computer is able to solve some of the NP-class problems in polynomial time. A hardware approach to modeling quantum computing is considered, and a general mathematical model of the operation of a quantum computer is described, and a technique for mathematical modeling of quantum computing is presented. At the stage of consideration of the method of mathematical modeling, the most resource-intensive parts of the model are indicated. Also, issues related to data parallelization on a hardware accelerator, which are planned to be used to simulate quantum computing, were considered, and algorithms for the operation of this type of accelerator were given. A more compact data format is proposed, which is recommended to be used when implementing the accelerator. Using the proposed format, it is possible to reduce the resources spent on elementary arithmetic operations. The possibility of introducing an optimization algorithm to minimize the time spent in computations, as well as to speed up the execution of quantum algorithms in simulators of a quantum computer at the stage of the effect of quantum gates on the quantum register model, is proposed. The results of the optimization algorithm and its comparison with the classical mathematical approach using a software model are presented.
During the study, software techniques for optimizing the quantum computer model were considered. The main goal of techniques that increase the efficiency of modeling is to reduce the amount of data that must be processed when modeling quantum gates. The most suitable algorithm for implementing a hardware accelerator was considered and modeled in the experimental part. Algorithms of graph theory or decision diagrams are not very suitable for this task, since their implementation will require the implementation of tensor matrix products, which is more convenient to do on a software simulator. It is also worth noting the increasingly growing interest in modeling quantum computing on special hardware, such as video cards or supercomputers. Therefore, the technique presented in the work is relevant, because it combines software solutions in the field of optimization over the past few years and recently studied methods for modeling quantum computing.
Currently, the theory of quantum computing is actively developing. Despite the fact that a quantum computer has some features, any algorithm designed for a classical computer can be implemented for a quantum one. The relevance of the topic of quantum computers is confirmed by the fact that even now banking systems, cryptography and encryption of information require enormous resources of computing systems, these are just some examples, but the most important and vivid ones that relate to the everyday life of a huge part of the world's population. A hardware computing core has been developed and simulated, which is the main part of an accelerator based on field-programmable gate array with computer aided design Altera Quartus. Considering the obtained time dependence of the number of cycles required for the impact of a single-qubit quantum gate on a quantum register on the number of qubits and parallel arithmetic logic units in the hardware computing core, when simulating quantum computing, a method was developed to determine the increase in hardware performance and ways to improve the performance of an accelerator based on a hardware computing core were developed. based on field-programmable gate array.
In the past few decades the problem of creating quantum computer is one of the most important. Quantum computer uses the quantum mechanics such as quantum parallelism and quantum entanglement. Using this mechanisms quantum computer is able to solve some of the problems of NP-class in polynomial time. In our days the prototypes of such class of devices are created, but they cant be used for effective solving of the planned problems because of difficulties of realization. However, mathematical apparatus that describes the behavior of quantum particles using wave function exists. This apparatus allows creating algorithms that can be effectively solved only on quantum computer. Hence its a problem of investigation of effectiveness of new quantum algorithms. The only option is modeling quantum system on classical devices. But the quantum system cant be modeled effectively on classical devices, hence its suggested to use methodic of accelerating of modeling of quantum computing.
At all stages of the development of information technology, much attention has been paid tothe issues of modeling functioning specialized high-performance computing systems, which make itpossible to provide the necessary performance indicators in combination with minimized costs ofsoftware resources and energy consumption. The developed information system, focused on human-machine interaction, allows you to clearly see the strengths and weaknesses of the developedquantum computing device, to prove the advantages of its use. The developed modeling informationsystem is a visual aid for understanding the main methods of interaction between informationprocesses and information resources. A number of the most important problems cannot besolved using classical computers, including classical supercomputers, in a reasonable time. Recently,there has been a surge in interest in quantum computers. This article is devoted to solvingthe problem of research and development of a circuit and a simulation technique for a hardwareaccelerator of quantum computing. The work touches upon the problems of research and development of methods for the functioning of quantum circuits and models of quantum computing devices.The relevance of these studies lies in the mathematical and software modeling and implementationof the fundamental components of quantum computing models. The scientific novelty ofthis direction is expressed in the optimization of the quantum computational process. The scientificnovelty of this area is primarily expressed in the constant updating and supplementing of the fieldof quantum research in a number of areas. The aim of this work is to implement a technique forconstructing a hardware accelerator. The technical support of the information quantum systemand processes has been implemented, including new software for the transmission and presentationof information. The use of a quantum computing information system differs from its counterpartsby a significant increase in the speed of solving computational problems and, most importantly,by an exponential increase in the speed of solving NP-complete problems that can besolved on classical machines in unacceptable time. Due to the fact that the class of NP problems iswide, the applicability and significance of the developed method for constructing a modular systemof quantum computing is beyond doubt.