Quantum computing has the potential to transform modern computation by offering exponential advantages in areas such as cryptography, optimization, and intelligent data processing. To effectively realize these advantages, particularly in fault-tolerant and Noisy Intermediate-Scale Quantum (NISQ) environments, quantum circuits must be both resource-efficient and error-resilient. This paper presents a novel Binary-Coded Decimal (BCD) to Excess-3 code converter designed exclusively using the Clifford+T gate set, which is widely supported by fault-tolerant quantum hardware. The proposed design eliminates conventional 4-bit reversible adder-based implementations and instead employs an optimized logic structure based on Clifford+T-decomposed Peres gates. By leveraging Temporary Logical-AND gates and CNOT operations, the circuit achieves reduced T-count, circuit depth, and quantum cost as key metrics in fault-tolerant quantum computation. Functional correctness is verified through IBM Qiskit, Version 2.1 simulations for all valid BCD inputs. The proposed converter serves as a scalable and hardware-compatible arithmetic building block for resource-aware and AI-oriented quantum architectures.
Universal fault-tolerant quantum computers will require the use of efficient protocols to implement encoded operations necessary in the execution of algorithms. In this work, we show how SMT solvers can be used to automate the construction of Clifford circuits with certain fault-tolerance properties and we apply our techniques to a fault-tolerant magic-state-preparation protocol. Part of the protocol requires converting magic states encoded in the color code to magic states encoded in the surface code. Since the teleportation step involves decoding a color code merged with a surface code, we develop a decoding algorithm that is applicable to such codes.
Flagging the Clifford hierarchy:~Fault-tolerant logical
2lπ rotations via measuring circuit gauge operators of non-Cliffords
We provide a recursively defined sequence of flag circuits which will detect logical errors induced by non-fault-tolerant
RZ(2lπ) gates on CSS codes with a fault distance of two. As applications, we give a family of circuits with
O(l) gates and ancillae which implement fault-tolerant logical
RZ(2lπ) or
RZZ(2lπ) gates on any
[[k+2,k,2]] iceberg code and fault-tolerant circuits of size
O(l) for preparing
∣2lπ⟩ resource states in the
[[7,1,3]] code, which can be used to perform fault-tolerant
RZ(2lπ) rotations via gate teleportation, allowing for implementations of these gates that bypass the high overheads of gate synthesis when
l is small relative to the precision required. We show how the circuits above can be generalized to
π(x0.x1x2…xl)=∑jlπ2jxj rotations with identical overheads in
l, which could be useful in quantum simulations where time is digitized in binary. Finally, we illustrate two approaches to increase the fault-distance of our construction. We show how to increase the fault distance of a Cliffordized version of the T gate circuit to
3 in the Steane code and how to increase the fault-distance of the
2π iceberg circuit to
4 through concatenation in two-level iceberg codes. This yields a targeted logical
RZ(2π) gate with fault distance
4 on any row of logical qubits in an
[[(k2+2)(k1+2),k1k2,4]] code.