Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Institute of Physics eBooks

Quantum adder circuits

Hafiz Md. Hasan Babu

Published May 1, 2020• 0 citations
Publisher
DOI
10.1088/978-0-7503-2747-3ch6

Related papers

Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing

Nusrat Jahan Lisa, Hafiz Md. Hasan Babu

In this paper, we present an optimized design for the quantum ternary adder/subtract or circuit. We propose the design of quantum Ternary Peres Gate (TPG). The design of our proposed quantum ternary adder/subtract or circuit consists of two parts: a) Firstly, it has the design of a quantum ternary full-adder circuit using the proposed TPG gates, and b) Secondly, it designs the proposed adder/subtract or circuit by using the constructed full-adder in a) and M-S gates. We also propose a heuristic to design a compact ternary adder/subtract or circuit. Our circuits perform much better than the existing ones.

IEEE International Symposium on Multiple-Valued Logic (ISMVL)•May 1, 2015•16 citations

Quantum Circuits

Colin P. Williams

Texts in computer science•Dec 6, 2010•0 citations

Quantum Combinational Circuits

Hafiz Md. Hasan Babu

Springer eBooks•Jan 1, 2025•0 citations

The quantum adder circuits

Hafiz Md. Hasan Babu

This chapter presents the design of a quantum adder circuit which is optimized in terms of quantum cost. The four-bit quantum carry skip adder and eight-bit quantum carry skip adder circuits are described in this chapter.

Institute of Physics eBooks•Jun 1, 2023•0 citations

Understand Noise on Universal Quantum Adder Circuit

Wiphoo Methachawalit, Prabhas Chongstitvatana

Quantum Fourier Transform (QFT) is an essential algorithm for quantum computers. There are many uses of QFT in the application of quantum computing. In this work, we proposed a generalized adder circuit that was fundamental for QFT. We designed and ran the experiments with the proposed adder circuit on an IBM quantum computer facility. We observed that the number of qubits was one factor in the error rate. We found that our proposed two-qubits adder circuit running on the IBM quantum computer had an error rate of around 25%. The complexity of the adder circuit includes qubit connectivity, physical devices, and error from noise due to the environment. We demonstrated the constraints of the proposed adder circuit.

Current Applied Science and Technology•Dec 14, 2023•0 citations

Quantum circuits

Dipankar Bhattacharyya, Jyotirmoy Guha

Institute of Physics eBooks•Jan 1, 2022•0 citations
In this paper, we present an optimized design for the quantum ternary adder/subtract or circuit. We propose the design of quantum Ternary Peres Gate (TPG). The design of our proposed quantum ternary adder/subtract or circuit consists of two parts: a) Firstly, it has the design of a quantum ternary full-adder circuit using the proposed TPG gates, and b) Secondly, it designs the proposed adder/subtract or circuit by using the constructed full-adder in a) and M-S gates. We also propose a heuristic to design a compact ternary adder/subtract or circuit. Our circuits perform much better than the existing ones.
Quantum Fourier Transform (QFT) is an essential algorithm for quantum computers. There are many uses of QFT in the application of quantum computing. In this work, we proposed a generalized adder circuit that was fundamental for QFT. We designed and ran the experiments with the proposed adder circuit on an IBM quantum computer facility. We observed that the number of qubits was one factor in the error rate. We found that our proposed two-qubits adder circuit running on the IBM quantum computer had an error rate of around 25%. The complexity of the adder circuit includes qubit connectivity, physical devices, and error from noise due to the environment. We demonstrated the constraints of the proposed adder circuit.