Throughout this Ph.D., the quest to build a quantum computer has accelerated, driven by ever-improving fidelities of conventional qubits and the development of new technologies that promise topologically protected qubits with the potential for lifetimes that exceed those of comparable conventional qubits. As such, there has been an explosion of interest in the design of an architecture for a quantum computer. This design would have to include high-quality qubits at the bottom of the stack, be extensible, and allow the layout of many qubits with scalable methods for readout and control of the entire device. Furthermore, the whole experimental infrastructure must handle the requirements for parallel operation of many qubits in the system. Hence the crux of this thesis: to design an architecture for a semiconductor-based quantum computer that encompasses all the elements that would be required to build a large scale quantum machine, and investigate the individual these elements at each layer of this stack, from qubit to readout to control.
Throughout this Ph.D., the quest to build a quantum computer has accelerated, driven by ever-improving fidelities of conventional qubits and the development of new technologies that promise topologically protected qubits with the potential for lifetimes that exceed those of comparable conventional qubits. As such, there has been an explosion of interest in the design of an architecture for a quantum computer. This design would have to include high-quality qubits at the bottom of the stack, be extensible, and allow the layout of many qubits with scalable methods for readout and control of the entire device. Furthermore, the whole experimental infrastructure must handle the requirements for parallel operation of many qubits in the system. Hence the crux of this thesis: to design an architecture for a semiconductor-based quantum computer that encompasses all the elements that would be required to build a large scale quantum machine, and investigate the individual these elements at each layer of this stack, from qubit to readout to control.
Building a quantum computer is not only about having qubits or quantum processors, analogously to classical computers are not only based on transistors or integrated circuits. Accordingly, in the very recent times, a few unique research groups in academia and companies have been exploring and proposing high-level and low-level programming languages, compilers, microarchitecture and instruction set architectures for quantum computation as well as different computer architecture approaches. In other words, developing a quantum computer requires bridging quantum applications and quantum devices. This talk will address the main challenges of building a scalable full-stack quantum computing system followed by a discussion on its architecture focusing on fault tolerance and compilation of quantum algorithms on NISQ devices. I will also provide my vision on how the research community could accelerate the process towards building such a scalable quantum machine, potentially through vertical cross-layer co-design structured methodologies.
For the realization of a quantum computer, a good qubit design as the basic building block is a nontrivial starting point. To fully leverage the potential of quantum computing, quantum processors will likely have to incorporate billions of high-quality qubits. Several approaches are being pursued and exhibit different strength and weaknesses. The device concepts and fabrication procedures for semiconductor based qubits are very similar to those used in the semiconductor industry. Using the spin-degree of freedom, their coherence properties and the quality of single-qubit operations have now reached the required level and are on par with competing approaches. Two-qubit operations will likely follow suit in the near future. With these basic requirements being met, it is now time to think if and how increasingly large multi-qubit systems and eventually functional quantum processor can be realized. This quest raises many pertinent questions, some of which equally apply to other qubit platforms. How reproducibly can the different types of semiconductor qubits be produced? How can their operating point be adjusted efficiently and in an automated way? How can they be connected to form meaningful multi-qubit circuits? How severe are multi-qubit control issues such as crosstalk and frequency crowding, and how can they be avoided? What control system architectures are most suitable for operating large numbers of qubits? What is the limit of cryogenic electronics regarding power consumption and integration density? This paper gives a (partial) overview of the state of the art in the field and discusses future challenges associated with the realization of large-scale quantum processors, many of which will greatly benefit from input from engineering science. The guiding vision is that of a highly integrated quantum processor with an ultra-low power cryogenic control system.
In the span of four decades, quantum computation has evolved from an intellectual curiosity to a potentially realizable technology. Today, small-scale demonstrations have become possible for quantum algorithmic primitives on hundreds of physical qubits. Nevertheless, there are significant outstanding challenges in quantum hardware, fabrication, software architecture, and algorithms on the path towards a full-stack scalable quantum computing technology. Here, we provide a comprehensive review of these scaling challenges. We show how to facilitate scaling by adopting existing semiconductor technology to build much higher-quality qubits, employing systems engineering approaches, and performing distributed heterogeneous quantum-classical computing. We provide a detailed resource and sensitivity analysis for quantum applications on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors. We provide comprehensive resource estimates for several utility-scale applications including quantum chemistry calculations, catalyst design, NMR spectroscopy, and Fermi-Hubbard simulation. We show that orders of magnitude enhancement in performance could be obtained by a combination of hardware improvements and tight quantum-HPC integration. Furthermore, we introduce high-performance architectures for quantum-probabilistic computing with custom-designed accelerators to tackle today's industry-scale classical optimization, machine learning, and quantum simulation tasks in a cost-effective manner.
Semiconductors, a significant type of material in the information era, are becoming more and more powerful in the field of quantum information. In recent decades, semiconductor quantum computation was investigated thoroughly across the world and developed with a dramatically fast speed. The research varied from initialization, control and readout of qubits, to the architecture of fault-tolerant quantum computing. Here, we first introduce the basic ideas for quantum computing, and then discuss the developments of single- and two-qubit gate control in semiconductors. Up to now, the qubit initialization, control and readout can be realized with relatively high fidelity and a programmable two-qubit quantum processor has even been demonstrated. However, to further improve the qubit quality and scale it up, there are still some challenges to resolve such as the improvement of the readout method, material development and scalable designs. We discuss these issues and introduce the forefronts of progress. Finally, considering the positive trend of the research on semiconductor quantum devices and recent theoretical work on the applications of quantum computation, we anticipate that semiconductor quantum computation may develop fast and will have a huge impact on our lives in the near future.
Utility-scale quantum computing requires the integration and operation of a large-scale qubit register. Semiconductor spin qubits are a primary candidate for this, due to the prospects of building integrated hybrid quantum-classical architectures. However, scaling spin-qubit systems while preserving performance and control has remained a challenge. Here, we demonstrate the operation of an 18-qubit array in germanium based on an extendable 2xN architecture. We achieve simultaneous initialization, control, and readout across the entire array, enabled by parallel operation of modular unit cells. Across the array, we achieve average and median single-qubit gate fidelities of 99.8% and 99.9%, respectively. Finally, we characterize the nearest-neighbor exchange couplings throughout the device and implement high-quality controlled-Z gates to generate a three-qubit Greenberger-Horne-Zeilinger (GHZ) state. These results demonstrate that spin-qubit arrays can be scaled while maintaining high-fidelity operation and establish a modular, extendable architecture for planar semiconductor quantum processors.
A quantum machine may solve some complex problems that are intractable for even the most powerful classical computers. By exploiting quantum superposition and entanglement phenomena, quantum algorithms can achieve from polynomial to exponential speed up when compared to their best classical counterparts. A quantum computer will be a part of a heterogeneous, multi-core computer in which a classical processor will interact with several accelerators such as FPGAs, GPUs and also a quantum co-processor. Figure 1 shows the different layers of the quantum computer system stack [1]. Building such a quantum system requires contributions from different fields such as physics, electronics, computer science and computer engineering for addressing the following challenges: i) build scalable quantum chips integrating qubits with long coherence times and high-fidelity operations, ii) develop classical control electronics at possibly cryogenic temperatures and iii) create the microarchitecture as well as the software for quantum computation.