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IEEE International Conference on Electronics and Communication Engineering (ICECE)

Parallel Algorithmic Optimization for Enhanced Quasi-Maximum Likelihood Decoding on GPU

Kong Fei-Yue, Sijing Chen, Xue-fen Wan, Yang Yi

Published Dec 1, 2019• 0 citations
Publisher

Abstract

The Enhanced quasi-maximum likelihood (EQML) decoder has better decoding performance than the traditional belief propagation (BP) decoder, but its decoding speed is greatly reduced due to its complicated computational structure. Therefore, an efficient graphics processing unit (GPU) implementation structure for EQML decoder of low-density parity-check (LDPC) code is proposed. Intra-codeword parallel and inter-codeword parallel decoding schemes on GPU are adopted instead of serial decoding on CPU. Several optimization methods have also been employed to enhance the decoder throughput, such as compressed storing and Kernel thread arrangement scheme, which improve the decoding speed without degrading the decoding performance of the decoder. Experiment results show that our GPU based implementation structure which is about two orders of magnitude faster than that of CPU implementation.

DOI
10.1109/icece48499.2019.9058555

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The Enhanced quasi-maximum likelihood (EQML) decoder has better decoding performance than the traditional belief propagation (BP) decoder, but its decoding speed is greatly reduced due to its complicated computational structure. Therefore, an efficient graphics processing unit (GPU) implementation structure for EQML decoder of low-density parity-check (LDPC) code is proposed. Intra-codeword parallel and inter-codeword parallel decoding schemes on GPU are adopted instead of serial decoding on CPU. Several optimization methods have also been employed to enhance the decoder throughput, such as compressed storing and Kernel thread arrangement scheme, which improve the decoding speed without degrading the decoding performance of the decoder. Experiment results show that our GPU based implementation structure which is about two orders of magnitude faster than that of CPU implementation.
The Enhanced Quasi-Maximum Likelihood(EQML) decoder has better decoding performance for short Low Density Parity Check(LDPC) codes than traditional Belief Propagation(BP) decoder,and can meet the high reliability requirements of 5G mobile communication.However,its decoding speed is greatly reduced due to its complex computational structure.To address the problem,this paper proposes a parallel acceleration scheme based on Graphics Processing Unit(GPU) for EQML decoder.The scheme compresses and stores the parity check matrix of irregular LDPC codes,and resorts the traditional BP decoding algorithms to maximize the utilization of threads in Kernel.Then parallel decoding is implemented for multi-code words in each stage of reprocessing,so as to realize memory access optimization and parallel decoding of streams.Experimental results show that the GPU-based EQML decoder improves the speed by two orders of magnitude compared with the CPU-based decoder,while keeping the error correction performance.
This paper presents an efficient implementation of a parallel block-layered nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) decoder on a graphics processing unit (GPU) to achieve significant improvements in both flexibility and scalability. An efficient block-layered scheme and a data structure suitable for parallel computing are proposed to perform decoding on the GPU. The scheme is applied to a min-max decoding algorithm that exploits the inherent massive parallelization capabilities of NB-QC-LDPC decoder. The results of the proposed approach demonstrate that the layered scheme can be efficiently implemented in a GPU device. Moreover, experimental results show that the proposed GPU-based block-layered NB-QC-LDPC decoder provides a faster decoding runtime compare to CPU-based implementation and obtains a coding gain under a low 10-10 BER and low 10-7 FER.
In this paper, efficient LDPC block-code decoders/simulators which run on graphics processing units (GPUs) are proposed. We also implement the decoder for the LDPC convolutional code (LDPCCC). The LDPCCC is derived from a predesigned quasi-cyclic LDPC block code with good error performance. Compared to the decoder based on the randomly constructed LDPCCC code, the complexity of the proposed LDPCCC decoder is reduced due to the periodicity of the derived LDPCCC and the properties of the quasicyclic structure. In our proposed decoder architecture, Γ (Γ is a multiple of a warp) codewords are decoded together, and hence, the messages of Γ codewords are also processed together. Since all the Γ codewords share the same Tanner graph, messages of the Γ distinct codewords corresponding to the same edge can be grouped into one package and stored linearly. By optimizing the data structures of the messages used in the decoding process, both the read and write processes can be performed in a highly parallel manner by the GPUs. In addition, a thread hierarchy minimizing the divergence of the threads is deployed, and it can maximize the efficiency of the parallel execution. With the use of a large number of cores in the GPU to perform the simple computations simultaneously, our GPU-based LDPC decoder can obtain hundreds of times speedup compared with a serial CPU-based simulator and over 40 times speedup compared with an eight-thread CPU-based simulator.
A flexible and scalable approach for LDPC decoding on CUDA based Graphics Processing Unit (GPU) is presented in this paper. Layered decoding is a popular method for LDPC decoding and is known for its fast convergence. However, efficient implementation of the layered decoding algorithm on GPU is challenging due to the limited amount of data-parallelism available in this algorithm. To overcome this problem, a kernel execution configuration that can decode multiple codewords simultaneously on GPU is developed. This paper proposes a compact data packing scheme to reduce the number of global memory accesses and parity-check matrix representation to reduce constant memory latency. Global memory bandwidth efficiency is improved by coalescing simultaneous memory accesses of threads in a half-warp into a single memory transaction. Asynchronous data transfers are used to hide host memory latency by overlapping kernel execution with data transfers between CPU and GPU. The proposed implementation of LDPC decoder on GPU performs two orders of magnitude faster than the LDPC decoder on a CPU and four times faster than the previously reported LDPC decoder on GPU. This implementation achieves a throughput of 160Mbps, which is comparable to dedicated hardware solutions.
Low-Density Parity-Check (LDPC) codes are powerful error correcting codes (ECC). They have recently been adopted by several data communication standards such as DVB-S2 and WiMax. LDPCs are represented by bipartite graphs, also called Tanner graphs, and their decoding demands very intensive computation. For that reason, VLSI dedicated architectures have been investigated and developed over the last few years. This paper proposes a new approach for LDPC decoding on graphics processing units (GPUs). Efficient data structures and an new algorithm are proposed to represent the Tanner graph and to perform LDPC decoding according to the stream-based computing model. GPUs were programmed to efficiently implement the proposed algorithms by applying data-parallel intensive computing. Experimental results show that GPUs perform LDPC decoding nearly three orders of magnitude faster than modern CPUs. Moreover, they lead to the conclusion that GPUs with their tremendous processing power can be considered as a consistent alternative to state-of-the-art hardware LDPC decoders.
An efficient parallel simulation scheme of quasi-cyclic (QC) low-density parity-check (LDPC) decoding is proposed to improve the simulation efficiency greatly. It employs multi-threads with the multi-processors of a graphic processing unit (GPU) to perform the simulation of LDPC decoding in parallel. Other than full hardware based LDPC decoding, it obtains good features of low cost, easy programming complexity by using the compute unified device architecture (CUDA) techniques. The CUDA also provides parallel computing by the GPU with efficient multi-thread computation and very high memory bandwidth. Based on the proposed scheme, all bit nodes or check nodes can be updated in an LDPC decoding iteration simultaneously. Therefore, it provides an efficient and fast approach of QC LDPC decoding.