Abstract The potential of achieving computational hardware with quantum advantage depends heavily on the quality of quantum gate operations. However, the presence of imperfect two-qubit gates poses a significant challenge and acts as a major obstacle in developing scalable quantum information processors. Google’s Quantum AI and collaborators claimed to have conducted a supremacy regime experiment. In this experiment, a new two-qubit universal gate called theSycamoregate is constructed and employed to generate random quantum circuits (RQCs), using a programmable quantum processor with 53 qubits. These computations were carried out in a computational state space of size
9×1015 9×1015 . Nevertheless, even in strictly-controlled laboratory settings, quantum information on quantum processors is susceptible to various disturbances, including undesired interaction with the surroundings and imperfections in the quantum state. To address this issue, we conduct both quantum state tomography (QST) and quantum process tomography (QPT) experiments on Google’sSycamoregate using different artificial architectural superconducting quantum computer. Furthermore, to demonstrate how errors affect gate fidelity at the level of quantum circuits, we design and conduct full QST experiments for the five-qubit eight-cycle circuit, which was introduced as an example of the programability of Google’sSycamorequantum processor. These quantum tomography experiments are conducted in three distinct environments: noise-free, noisy simulation, and on IBM Quantum’s genuine quantum computer. Our results offer valuable insights into the performance of IBM Quantum’s hardware and the robustness ofSycamoregates within this experimental setup. These findings contribute to our understanding of quantum hardware performance and provide valuable information for optimizing quantum algorithms for practical applications.
Fixed-frequency superconducting quantum processors are one of the most mature quantum computing architectures with high-coherence qubits and simple controls. However, high-fidelity multiqubit gates pose tight requirements on individual qubit frequencies in these processors, and these constraints are difficult to satisfy when constructing larger processors due to the large dispersion in the fabrication of Josephson junctions. In this paper, we propose a mixed-integer-programming-based optimization approach that determines qubit frequencies to maximize the fabrication yield of quantum processors. We study traditional qubit and qutrit (three-level) architectures with cross-resonance interaction processors. We compare these architectures to a differential ac-Stark shift based on entanglement gates and show that our approach greatly improves the fabrication yield and also increases the scalability of these devices. Our approach is general and can be adapted to problems where one must avoid specific frequency collisions.
Single-qubit gates on superconducting quantum processors are typically implemented using microwave pulses applied through dedicated control lines. However, these microwave pulses may also drive other qubits due to crosstalk arising from capacitive coupling and wavefunction overlap in systems with closely spaced transition frequencies. Crosstalk and frequency crowding increase errors during simultaneous single-qubit operations relative to isolated gates, thus forming a major bottleneck for scaling superconducting quantum processors. In this work, we combine model-based qubit frequency optimization with pulse shaping to demonstrate crosstalk error mitigation in single-qubit gates on a 49-qubit superconducting quantum processor. We introduce and experimentally verify an analytical model of simultaneous single-qubit gate error caused by microwave crosstalk that depends on a given pulse shape. By employing a model-based optimization strategy of qubit frequencies, we minimize the crosstalk-induced error across the processor and achieve a mean simultaneous single-qubit gate fidelity of 99.96% for a 16-ns gate duration, approaching the mean individual gate fidelity. To further reduce the simultaneous error and required qubit frequency bandwidth on high-crosstalk qubit pairs, we introduce a crosstalk transition suppression (CTS) pulse shaping technique that minimizes the spectral energy around transitions inducing leakage and crosstalk errors. Finally, we combine CTS with model-based frequency optimization across the device and experimentally show a systematic reduction in the required qubit frequency bandwidth for high-fidelity simultaneous gates, supported by simulations of systems with up to 1000 qubits. By alleviating constraints on qubit frequency bandwidth for parallel single-qubit operations, this work represents an important step for scaling towards larger quantum processors.