We demonstrate high-fidelity logical qubit operations using \texttt{ibm\_phoenix}, a square-lattice array of 120 coupled superconducting qubits that are capable of fast reset. Using strategies to exclude underperforming components together with noise informed decoding, we routinely produce surface codes at distance-3 and distance-5 with logical error per round below 1\%. We demonstrate entanglement between two logical qubits, where logical Bell-state fidelities above 93\% are observed for entanglement created via lattice surgery. With three logical qubits and lattice surgery, we perform logical teleportation of a range of states and gates, observing fidelities in the range 78\% - 93\%. Using reset to reduce qubit leakage, we show that repeated rounds of stabilizer measurements continue to exhibit improvements in a stability experiment up to $\sim 2\cdot 10^{-7}$ over 170 measurement rounds.We demonstrate high-fidelity logical qubit operations using \texttt{ibm\_phoenix}, a square-lattice array of 120 coupled superconducting qubits that are capable of fast reset. Using strategies to exclude underperforming components together with noise informed decoding, we routinely produce surface codes at distance-3 and distance-5 with logical error per round below 1\%. We demonstrate entanglement between two logical qubits, where logical Bell-state fidelities above 93\% are observed for entanglement created via lattice surgery. With three logical qubits and lattice surgery, we perform logical teleportation of a range of states and gates, observing fidelities in the range 78\% - 93\%. Using reset to reduce qubit leakage, we show that repeated rounds of stabilizer measurements continue to exhibit improvements in a stability experiment up to $\sim 2\cdot 10^{-7}$ over 170 measurement rounds.

quant-pharXiv:2610.32347Oct 26, 20260 citations

Error-Transparent Quantum Gates for Small Logical Qubit Architectures

Eliot Kapit

One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.

arXiv:1703.09762Physical Review LettersFeb 1, 201837 citations

Stabilization and operation of a Kerr-cat qubit

A. Grimm, N. E. Frattini, Shruti Puri +6 more

arXiv:1907.12131NatureAug 12, 2020476 citations

Improved autonomous error correction using variable dissipation in small logical qubit architectures

David Rodríguez Pérez, Eliot Kapit

Abstract Coherence times for superconducting qubits have greatly improved over time. Moreover, small logical qubit architectures using engineered dissipation have shown great promise for further improvements in the coherence of a logical qubit manifold comprised of few physical qubits. Nevertheless, optimal working parameters for small logical qubits are generally not well understood. This work presents several approaches to finding preferential parameter configurations by looking at three different cases of increasing complexity. We begin by looking at state stabilization of a single qubit using dissipation via coupling to a lossy object. We look at the limiting factors in this approach to error correction, and how we address those by numerically optimizing the parametric coupling strength with the lossy object having an effective time-varying dissipation rate—we call this a pulse-reset cycle. We then translate this approach to more efficient state stabilization to an abstracted three-qubit flip code, and end by looking at the very small logical qubit (VSLQ). By using these techniques, we can further increase logical state lifetimes for different architectures. We show significant advantages in using a pulse-reset cycle over numerically optimized, fixed parameter spaces.Abstract Coherence times for superconducting qubits have greatly improved over time. Moreover, small logical qubit architectures using engineered dissipation have shown great promise for further improvements in the coherence of a logical qubit manifold comprised of few physical qubits. Nevertheless, optimal working parameters for small logical qubits are generally not well understood. This work presents several approaches to finding preferential parameter configurations by looking at three different cases of increasing complexity. We begin by looking at state stabilization of a single qubit using dissipation via coupling to a lossy object. We look at the limiting factors in this approach to error correction, and how we address those by numerically optimizing the parametric coupling strength with the lossy object having an effective time-varying dissipation rate—we call this a pulse-reset cycle. We then translate this approach to more efficient state stabilization to an abstracted three-qubit flip code, and end by looking at the very small logical qubit (VSLQ). By using these techniques, we can further increase logical state lifetimes for different architectures. We show significant advantages in using a pulse-reset cycle over numerically optimized, fixed parameter spaces.

arXiv:2006.12633Quantum Science and TechnologyOct 22, 20204 citations

\sim 2\cdot 10^{-7}

over 170 measurement rounds.