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Physical Communication

Gradient-descent decoding of one-step majority-logic decodable codes

Anouar Yatribi, Mostafa Belkasmi, Fouad Ayoub

Published Jan 10, 2020• 6 citations
Publisher
DOI
10.1016/j.phycom.2019.100999

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This paper contains a survey on iterative decoders of low-density parity-check (LDPC) codes made of unreliable logic gates that are capable to provide lower probability of error, when compared to their perfectly reliable counterparts. We have recently shown that the error-floor performance of message-passing decoders can be improved, if randomness that exists in unreliable logic gates is incorporated into decoding deliberately, without any complexity cost. Furthermore, we have shown that controlling the level of unreliability enable us to exploit the stochastic resonance phenomenon, previously observed in theoretical physics, electronic and magnetic systems. In contrary to common belief, we have shown that for a narrow range of gate failure probability the overall decoding performance is dramatically increased. In this paper, we show that the effect of stochastic resonance is even more noticeable for the case of the gradient descent bit-flipping (GDBF) algorithm. This decoder combines the simplest iterative decoding algorithm with gradient descent optimization, making it an attractive solution for a variety of low complexity storage systems, or code-based cryptosystems. In addition, we show that getting the most of the stochastic resonance is essentially a deep learning problem, since setting the levels of unreliability for individual parts of the decoder by a training process is a step toward incorporating the machine learning techniques into design and analysis of iterative decoders of LDPC codes.
It is known that the Gradient descent bit flipping (GDBF) algorithm is an effective hard-decision decoding algorithm for low-density parity-check (LDPC) codes. However, trapping in a local maximum limits its error-rate performance. This paper presents a modified GDBF scheme that can mitigate the trapping problem and hence can improve the error-rate performance. Compared to the conventional GDBF algorithm, the proposed method is able to improve the decoding performance of 0.3dB for an (18582, 16626) code. The (18582, 16626) LDPC decoder integrates 636k logic gates and achieves a throughput of 12.4 Gbps at a clock frequency of 200 MHz in a 90nm process.