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Modified Gradient Descent Bit-Flipping Decoding for Low-Density Parity-Check Codes

Hua Li, Hong Wei Ding, Linhua Zheng

Published May 25, 2017• 3 citations
Publisher
DOI
10.1007/s11277-017-4486-7

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IEEE International Symposium on Circuits and Systems proceedings•May 25, 2025•1 citation
It is known that the Gradient descent bit flipping (GDBF) algorithm is an effective hard-decision decoding algorithm for low-density parity-check (LDPC) codes. However, trapping in a local maximum limits its error-rate performance. This paper presents a modified GDBF scheme that can mitigate the trapping problem and hence can improve the error-rate performance. Compared to the conventional GDBF algorithm, the proposed method is able to improve the decoding performance of 0.3dB for an (18582, 16626) code. The (18582, 16626) LDPC decoder integrates 636k logic gates and achieves a throughput of 12.4 Gbps at a clock frequency of 200 MHz in a 90nm process.
Recently, modified noisy gradient descent bit flipping (MNGDBF) algorithms have been proposed to eliminate the Gaussian random generators required in the original noisy gradient descent bit flipping (NGDBF) algorithm for the decoding of low-density parity-check (LDPC) codes. In this paper, a platform has been established for the hardware implementation of the LDPC encoder, the Gaussian noise channel generator and the decoder using MNGDBF decoding algorithms based on the use of field programmable gate array (FPGA). With 6-bit quantization, results show that the error performance achieved by hardware experiments is similar to that obtained by floating-point computer simulations. Moreover, we propose a new MNGDBF algorithm, in which the flipping condition is determined with the help of the summation of all inversion functions. Experimental results show that the proposed algorithm has superior performance than the original MNGDBF algorithm.