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International Journal of Quantum Information

Design of quaternary quantum reversible half subtractor, full subtractor and n-qudit borrow ripple subtractor

Abdollah Norouzi Doshanlou, Majid Haghparast, Mehdi Hosseinzadeh, Midia Reshadi

Published Aug 1, 2019• 1 citation
Publisher

Abstract

In this paper, we proposed novel plans of quaternary quantum reversible half and full subtractor circuits. The subtractor element is the essential part of the ALU in the digital computational devices. Thus, the improvement of subtractor block has a significant impact on the overall system performance. According to the comparison results, the proposed quaternary quantum half and full subtractor circuits show tremendous improvement in quantum cost, hardware complexity, number of constant input and garbage output as compared to their counterparts. Moreover, for the first time, the quaternary quantum borrow ripple subtractor structure is realized using the proposed quaternary quantum half and full subtractor circuits.

DOI
10.1142/s0219749919500485

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In this paper, we proposed novel plans of quaternary quantum reversible half and full subtractor circuits. The subtractor element is the essential part of the ALU in the digital computational devices. Thus, the improvement of subtractor block has a significant impact on the overall system performance. According to the comparison results, the proposed quaternary quantum half and full subtractor circuits show tremendous improvement in quantum cost, hardware complexity, number of constant input and garbage output as compared to their counterparts. Moreover, for the first time, the quaternary quantum borrow ripple subtractor structure is realized using the proposed quaternary quantum half and full subtractor circuits.
One of the major problems in designing highly compact digital systems is the rate of power consumption and internal heat generated by the loss of information during the computation. The tendency of current circuit design technologies is towards Nanoscale. Quaternary reversible logic is an emerging technology for the future designing of the quantum systems since quantum reversible circuits can be realized in Nanoscales. The adder building block is an essential part of any computer system. This block must be designed efficiently. We proposed a new quaternary quantum reversible half adder with the quantum cost of 17 and a quaternary quantum reversible full adder with a quantum cost of 23. For the first time in the literature, we report that we proposed quaternary quantum reversible half adder as well as full adder with an optimum number of constant inputs. As the circuit lines in the domain of quantum computation are considered to be a very limited resource, the achievements in this paper are promising. The proposed circuits are efficient in terms of all figures of merits in comparison to the existing counterparts. To design these adder circuits, we used 1-qudit and 2-qudit quaternary gates.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.
This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU).
In [1] we have presented the reversible subtractor designs based on a new reversible TR gate (TR refers to Thapliyal Ranganathan). In [1] as the quantum gates implementation of the TR gate was not known, only the upper bound on the quantum cost of the reversible subtractors units were established. In this work, we present a new design of the reversible half subtractor based on the quantum gates implementation of the reversible TR gate. The reversible TR gate is designed from 2×2 quantum gates such as CNOT and Controlled-V and Controlled-V+gates. The design of the proposed reversible half subtractor is shown to be better than the design presented in [2], [1] in terms of the quantum cost and delay while maintaining the minimum number of garbage outputs. Further, we present a new design of the reversible full subtractor based on the proposed quantum gates implementation of the TR gate. The proposed reversible full subtractor is optimized in terms of quantum cost, delay and garbage outputs by utilizing the identity property of V and V+reversible gates. The proposed reversible full subtractor is shown to be better than the existing design reported in [3], [1]. The reversible subtractors proposed in this work will be useful in a number of digital signal processing applications.
Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.