The high resolution of multidimensional space-time measurements and enormity of data readout counts in applications such as particle tracking in high-energy physics (HEP) is becoming nowadays a major challenge. In this work, we propose combining dimension reduction techniques with quantum information processing for application in domains that generate large volumes of data such as HEP. More specifically, we propose using quantum wavelet transform (QWT) to reduce the dimensionality of high spatial resolution data. The quantum wavelet transform takes advantage of the principles of quantum mechanics to achieve reductions in computation time while processing exponentially larger amount of information. We develop simpler and optimized emulation architectures than what has been previously reported, to perform quantum wavelet transform on high-resolution data. We also implement the inverse quantum wavelet transform (IQWT) to accurately reconstruct the data without any losses. The algorithms are prototyped on an FPGA-based quantum emulator that supports double-precision floating-point computations. Experimental work has been performed using high-resolution image data on a state-of-the-art multinode high-performance reconfigurable computer. The experimental results show that the proposed concepts represent a feasible approach to reducing dimensionality of high spatial resolution data generated by applications such as particle tracking in high-energy physics.
The high resolution of multidimensional space-time measurements and enormity of data readout counts in applications such as particle tracking in high-energy physics (HEP) is becoming nowadays a major challenge. In this work, we propose combining dimension reduction techniques with quantum information processing for application in domains that generate large volumes of data such as HEP. More specifically, we propose using quantum wavelet transform (QWT) to reduce the dimensionality of high spatial resolution data. The quantum wavelet transform takes advantage of the principles of quantum mechanics to achieve reductions in computation time while processing exponentially larger amount of information. We develop simpler and optimized emulation architectures than what has been previously reported, to perform quantum wavelet transform on high-resolution data. We also implement the inverse quantum wavelet transform (IQWT) to accurately reconstruct the data without any losses. The algorithms are prototyped on an FPGA-based quantum emulator that supports double-precision floating-point computations. Experimental work has been performed using high-resolution image data on a state-of-the-art multinode high-performance reconfigurable computer. The experimental results show that the proposed concepts represent a feasible approach to reducing dimensionality of high spatial resolution data generated by applications such as particle tracking in high-energy physics.
With the promising advancement in quantum computing technology in the last decade, there is a strong motivation to find suitable applications for quantum algorithms and quantum computers. Domains such as High Energy Physics (HEP) have an enormous readout count of high-resolution data. Performing pattern recognition on this readout is computationally challenging and time-consuming because of the multi-dimensionality of the data. In this paper, we propose a methodology that employs quantum algorithms such as Quantum Wavelet Transform and Grover's search algorithm for timeefficient pattern recognition in data sets that are characterized by high spatial resolution and high dimensionality. The motivation behind using quantum algorithms is the potential speedup relative to classical methods, when performed by a quantum computer. In our proposed methodology, Quantum Wavelet Transform is performed on the high spatial resolution data to reduce its dimensionality while quantum Grover's search algorithm is employed to search for target patterns in the reduced data set. Performing the search operation on data with reduced spatial resolution, minimizes processing overheads and computation times. Moreover, use of quantum techniques yield faster results, compared to classical dimension reduction and search methods. We demonstrate the feasibility of the proposed methodology by emulating the quantum algorithms on classical hardware based on field programmable gate arrays (FPGAs). A high performance reconfigurable computer (HPRC) was used for the experimental evaluation. The obtained results are favorable towards our proposed approach.
The promises of advanced quantum computing technology have driven research in the simulation of quantum computers on classical hardware, where the feasibility of quantum algorithms for real-world problems can be investigated. In domains such as High Energy Physics (HEP) and Remote Sensing Hyperspectral Imagery, classical computing systems are held back by enormous readouts of high-resolution data. Due to the multi-dimensionality of the readout data, processing and performing pattern recognition operations for this enormous data are both computationally intensive and time-consuming. In this article, we propose a methodology that utilizes Quantum Haar Transform (QHT) and a modified Grover's search algorithm for time-efficient dimension reduction and dynamic pattern recognition in data sets that are characterized by high spatial resolution and high dimensionality. QHT is performed on the data to reduce its dimensionality at preserved spatial locality, while the modified Grover's search algorithm is used to search for dynamically changing multiple patterns in the reduced data set. By performing search operations on the reduced data set, processing overheads are minimized. Moreover, quantum techniques produce results in less time than classical dimension reduction and search methods. The feasibility of the proposed methodology is verified by emulating the quantum algorithms on classical hardware based on field programmable gate arrays (FPGAs). We present designs of the quantum circuits for multi-dimensional QHT and multi-pattern Grover's search. We also present two emulation techniques and the corresponding hardware architectures for this methodology. A high performance reconfigurable computer (HPRC) was used for the experimental evaluation, and high-resolution images were used as the input data set. Analysis of the methods and implications of the experimental results are discussed.
Algorithms such as quantum wavelet transform (QWT) can be utilized on quantum processors to gain significant speedup compared to their classical counterparts. Domains such as high-energy-physics and remote-sensing hyperspectral imagery require high compute capabilities and can benefit from applying QWT for dimension reduction of multidimensional data. However, quantum circuits for QWT include permutations that contribute to large overall circuit depth. Deep circuits pose a critical challenge for state-of-the-art quantum computers because of quantum decoherence. In this work, we propose QWT circuits, which are optimized in terms of circuit depth, to account for the effects of decoherence, and resulting in high fidelity and efficient implementation on quantum processors. We present the circuits in generalized forms and show that they can be used for multilevel decomposable, multidimensional wavelet operations. Experimental evaluation of the proposed circuits is performed through simulation using MATLAB and IBM-Q qasm, and implemented on a real 15-qubit quantum processor from IBM.
Abstract One of the challenges facing current Noisy-Intermediate-Scale-Quantum devices (NISQ) is achieving efficient quantum circuit measurement or readout. The process of extracting classical data from the quantum domain, termed in this work as quantum-to-classical (Q2C) data decoding, generally incurs significant overhead, since the quantum circuit needs to be sampled repeatedly to obtain useful data readout. In this paper, we propose and evaluate time-efficient and depth-optimized Q2C methods based on the multidimensional, multilevel-decomposable, quantum wavelet transform (QWT) whose packet and pyramidal forms are leveraged and optimized. We also propose a zero-depth technique that uses selective placement of measurement gates to perform the QWT operation. To demonstrate their efficiency, the proposed techniques are quantitatively evaluated in terms of execution time, circuit depth, and accuracy in comparison to existing Q2C techniques. Experimental evaluations of the proposed Q2C methods are performed using real high-resolution multispectral images on a 27-qubit state-of-the-art quantum computing device from IBM Quantum.
The general approach for emulating quantum algorithms on classical platforms has been through representing them as gate-based quantum circuits. However, direct implementation of quantum circuits significantly increases the hardware resource utilization and system latency of classical emulators. In this paper, we investigate multiple implementation models alternative to conventional emulation approaches, as feasible solutions to the scalability problem in classical emulation of quantum circuits. In the first model, the quantum circuit functionality is reduced to equivalent, arithmetic (multiply-and-accumulate) operations and combined with two computation methods, based on lookup and dynamic generation. In the second model, a kernel operation is extracted from the quantum circuit based on its functionality, and the kernel is iterated through all input quantum states. The proposed emulation models provide space and time optimizations, significantly reducing resource utilizations and latencies and improving scalability. We use these models to develop a highly scalable hardware emulator that is based on reconfigurable technology for efficient simulations of full quantum algorithms and circuits. Our hardware implementations support single precision floating point arithmetic for improved accuracy, and contain fully pipelined designs for high throughput. We investigate quantum algorithms such as quantum Fourier transform and quantum wavelet transform and explore different hardware architectures and optimizations. Experimental results and analysis are provided for the architectures in terms of resource consumption and emulation time. The experiments are carried out on a high-performance reconfigurable computing system and the obtained results show that the proposed emulator is feasible for running and testing a variety of quantum algorithms.
Quantum algorithms can be efficiently emulated on classical hardware such as field programmable gate arrays (FPGAs), achieving significant speedup over software simulations. However, the increase in the required hardware resources for emulating quantum systems becomes a critical limitation as the number of qubits is increased. In this paper, we propose a scalable emulation framework for modeling quantum algorithms on FPGAs that employs efficient resource scheduling such as space and space-time scheduling. In addition, full floating point precision arithmetic and dataflow non-linear (dynamic) pipelining are also used to achieve higher accuracy and higher throughput. We propose scalable and optimized hardware architectures for Quantum Fourier Transform (QFT) and Grover's search algorithm and demonstrate the scalability of our framework by scaling the system up to 5 fully-entangled qubits. A multi-node (multi-FPGA), state-of-the-art high-performance reconfigurable computer (HPRC) was used for implementation of the proposed architectures. Our experimental results show that by employing efficient resource scheduling techniques, the hardware resource constraints could be mitigated and the proposed emulation framework could be made feasible for emulation of more complex, larger-scale quantum algorithms while maintaining higher accuracy and throughput than existing work.