Scaling fault-tolerant quantum computing (FTQC) requires orchestrating millions of operations continuously across a tightly coupled classical-quantum control stack. A critical challenge in this orchestration is determining the optimal hardware-software boundary, i.e., the Quantum Instruction Set Architecture (QISA). We focus on cryogenic, fixed-connectivity qubit platforms, such as superconducting and topological Majorana qubits. For these, existing QISA choices either operate at too low a level, violating cryogenic thermal budgets at scale, or at too high a level, imposing unrealizable complexity on the control engine. To reason about these tradeoffs, we introduce the ARIES instruction set hierarchy, which categorizes QISAs into distinct abstraction levels. To systematically evaluate these levels, we develop an end-to-end evaluation toolflow featuring a cycle-accurate classical driver and hardware engine simulator. Using eight quantum applications across superconducting and topological qubit platforms, we measure instruction bandwidth, transceiver power dissipation, and measurement processing overheads. We demonstrate that while physical-level abstractions exceed the thermal limits of dilution refrigerators by orders of magnitude, canonical-level abstractions significantly underestimate hardware routing congestion and execution runtimes. Our Level 4 QISA (local logical operations) offers an optimal architectural balance. As quantum hardware platforms scale toward FTQC in the coming years, our findings provide concrete architectural guidance for the design of their classical control stacks and instruction interfaces.
Complex instruction set computing architecture for performing accurate quantum
Z rotations with less magic
We present quantum protocols for executing arbitrarily accurate
π/2k rotations of a qubit about its
Z axis. Reduced instruction set computing (\textsc{risc}) architectures typically restrict the instruction set to stabilizer operations and a single non-stabilizer operation, such as preparation of a "magic" state from which
T=Z(π/4) gates can be teleported. Although the overhead required to distill high-fidelity copies of this magic state is high, the subsequent quantum compiling overhead to realize
Z rotations in a \textsc{risc} architecture can be much greater. We develop a complex instruction set computing (\textsc{cisc}) architecture whose instruction set includes stabilizer operations and preparation of magic states from which
Z(π/2k) gates can be teleported, for
2≤k≤kmax. This results in a substantial overall reduction in the number of gates required to achieve a desired gate accuracy for
Z rotations. The key to our construction is a family of shortened quantum Reed-Muller codes of length
2k+2−1, whose magic-state distillation threshold shrinks with
k but is greater than 0.85% for
k≤6.