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Journal of Physics Conference Series

DESIGN OF PROBABILISTIC GRADIENT DESCENT BIT-FLIPPING USING LDPC CODES

Sridevi Chitti, Mandala Sravanthi

Published May 1, 2019• 0 citations
Publisher

Abstract

Abstract This paper manages the equipment usage of the as of late presented Probabilistic Gradient-Descent Bit Flipping (PGDBF) decoder. The PGDBF is another kind of hard-choice decoder for Low-Density Parity-Check (LDPC) code, with enhanced blunder adjustment execution because of the presentation of think arbitrary annoyance in the figuring units. In the PGDBF, the irregular bother works amid the bit-flipping venture, with the target to maintain a strategic distance from the fascination of alleged catching arrangements of the LDPC code. In this paper, we propose a capable mechanical assembly organizing which limits the favorable position overhead expected to execute the sporadic aggravations of the PGDBF. Our organizing relies on the usage of a Short Random Sequence (SRS) that is imitated to completely apply the PGDBF loosening up standards, and on an improvement of the most mind boggling pioneer unit.

DOI
10.1088/1742-6596/1228/1/012059

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Abstract This paper manages the equipment usage of the as of late presented Probabilistic Gradient-Descent Bit Flipping (PGDBF) decoder. The PGDBF is another kind of hard-choice decoder for Low-Density Parity-Check (LDPC) code, with enhanced blunder adjustment execution because of the presentation of think arbitrary annoyance in the figuring units. In the PGDBF, the irregular bother works amid the bit-flipping venture, with the target to maintain a strategic distance from the fascination of alleged catching arrangements of the LDPC code. In this paper, we propose a capable mechanical assembly organizing which limits the favorable position overhead expected to execute the sporadic aggravations of the PGDBF. Our organizing relies on the usage of a Short Random Sequence (SRS) that is imitated to completely apply the PGDBF loosening up standards, and on an improvement of the most mind boggling pioneer unit.
This paper deals with the hardware implementation of the recently introduced Probabilistic Gradient-Descent Bit-Flipping (PGDBF) decoder. The PGDBF is a new type of hard-decision decoder for Low-Density Parity-Check (LDPC) code, with improved error correction performance thanks to the introduction of deliberate random perturbation in the computing units. In the PGDBF, the random perturbation operates during the bit-flipping step, with the objective to avoid the attraction of so-called trapping-sets of the LDPC code. In this paper, we propose an efficient hardware architecture which minimizes the resource overhead needed to implement the random perturbations of the PGDBF. Our architecture is based on the use of a Short Random Sequence (SRS) that is duplicated to fully apply the PGDBF decoding rules, and on an optimization of the maximum finder unit. The generation of good SRS is crucial to maintain the outstanding decoding performance of PGDBF, and we propose two different methods with equivalent hardware overheads, but with different behaviors on different LDPC codes. Our designs show that the improved PGDBF performance gains can be obtained with a very small additional complexity, therefore providing a competitive hard-decision LDPC decoding solution for current standards.
This paper represents the concept of hard decision decoder in which PGDBF is suitable decoder for the basic model of hard-choice decoder as long as low-density parity check code (LDPC) which is increase the error correction. This design introduced dynamic architecture which reduce the capability of random disarrangement of the PGDBF. The design is working on the Short Random Sequence (SRS) that is replica cover on the PGDBF decoding guidelines. In each iteration flipping number of bits these are focusing on improvement in performance and decoding delay. The best SRS is essential to manage the well-known decoding achievement of PGDBF, we introduced two kind of access with same hardware categories, but various LDPC codes are perform different behaviors. In this design we are modifying small hardware decoding unit for obtaining a good decoding explanation for present and further purpose.
Probabilistic gradient descent bit-flipping (PGDBF) is the state-of-the-art hard-decision algorithm for decoding low-density parity-check (LDPC) codes on binary symmetric channel (BSC). However, there still exists a considerable performance gap between the PGDBF algorithm and soft-decision algorithms, especially in the error-floor region. To bridge this performance gap, a tabu-list aided PGDBF (T-PGDBF) algorithm is proposed in this paper. In the T-PGDBF algorithm, a tabu-list is employed to help the decoding escape from trapping sets, which is the main cause of the error-floor phenomenon. The bits which are flipped in the current iteration will be added to the tabu-list to prevent them being flipped in the next iteration. Simulation results show that the T-PGDBF algorithm offers a significant performance gain when compared to the PGDBF algorithm, which can reach that of soft-decision algorithms. We also present the hardware architecture to implement the T-PGDBF algorithm. Synthesis results show that the improved performance offered by the T-PGDBF algorithm can be obtained with a small hardware overhead.
In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.
Existing bit-flipping algorithms, when used for irregular low-density parity-check (LDPC) codes, often suffer from performance degradation due to the imbalance caused by the irregular codeword structure. To alleviate this problem, this paper presents a column-weighted probabilistic gradient-descent bit-flipping (CW-PGDBF) decoder for irregular LDPC codes. Different weighting factors are allocated to variable nodes with different column weights to solve the imbalance. Furthermore, a modified probabilistic flipping rule is employed to reduce the hardware complexity while maintaining the error-correction performance. Simulation results demonstrate that the proposed algorithm can achieve significantly improved performance compared with other BF-based algorithms for irregular codes. Additionally, a hardware architecture for the CW-PGDBF decoder is proposed with acceptable hardware overhead compared to the original PGDBF decoder.
The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder offers a significant improvement in decoding performance for Low-Density Parity-Check (LDPC) codes on Binary Symmetric Channel (BSC). However, this outstanding decoding performance comes along with a non-negligible extra hardware cost to realize the probabilistic behavior on top of the deterministic Gradient Descent Bit-Flipping (GDBF) decoder. This paper presents a novel solution to implement PGDBF decoder on Quasi-Cyclic LDPC codes. The proposed architecture takes advantage of the cyclic shift permutation nature of QC-LDPC and changes the message flow such that a probabilistic behavior is emulated without the cost of an actual probabilistic signal generator. It is shown that, the proposed architecture improves the PGDBF decoding performance with respect to the state-of-the-art implementation while reducing hardware complexity, even being lower than that of the deterministic GDBF. The efficiency of our proposed method is verified through the ASIC 90nm CMOS technology implementations and decoding simulations.