IEEE Computer Society Annual Symposium on VLSI

Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes

Changfu He, Keyue Deng, Suwen Song, Zhongfeng Wang

Published Jun 20, 2023• 3 citations

Abstract

Existing bit-flipping algorithms, when used for irregular low-density parity-check (LDPC) codes, often suffer from performance degradation due to the imbalance caused by the irregular codeword structure. To alleviate this problem, this paper presents a column-weighted probabilistic gradient-descent bit-flipping (CW-PGDBF) decoder for irregular LDPC codes. Different weighting factors are allocated to variable nodes with different column weights to solve the imbalance. Furthermore, a modified probabilistic flipping rule is employed to reduce the hardware complexity while maintaining the error-correction performance. Simulation results demonstrate that the proposed algorithm can achieve significantly improved performance compared with other BF-based algorithms for irregular codes. Additionally, a hardware architecture for the CW-PGDBF decoder is proposed with acceptable hardware overhead compared to the original PGDBF decoder.

DOI: 10.1109/isvlsi59464.2023.10238556

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