This study addresses the minor-embedding problem, which involves mapping the variables of an Ising model onto a quantum annealing processor. The primary motivation stems from the observed performance disparity of quantum annealers when solving problems suited to the processor's architecture versus those with non-hardware-native topologies. Our research has two main objectives: i) to analyze the impact of embedding quality on the performance of D-Wave Systems quantum annealers, and ii) to evaluate the quality of the embeddings generated by Minorminer, the standard minor-embedding technique in the quantum annealing literature, provided by D-Wave. Regarding the first objective, our experiments reveal a clear correlation between the average chain length of embeddings and the relative errors of the solutions sampled. This underscores the critical influence of embedding quality on quantum annealing performance. For the second objective, we evaluate Minorminer's embedding capabilities, the quality and robustness of its embeddings, and its execution-time performance on Erdös-Rényi graphs. We also compare its performance with Clique Embedding, another algorithm developed by D-Wave, which is deterministic and designed to embed fully connected Ising models into quantum annealing processors, serving as a worst-case scenario. The results demonstrate that there is significant room for improvement for Minorminer, suggesting that more effective embedding strategies could lead to meaningful gains in quantum annealing performance.
Quantum annealing provides a practical realization of adiabatic quantum computation and has emerged as a promising approach for solving large-scale combinatorial optimization problems. However, current devices remain constrained by sparse hardware connectivity, which requires embedding logical variables into chains of physical qubits. This embedding overhead limits scalability and reduces reliability as longer chains are more prone to noise-induced errors. In this work, we develop an embedding-aware baseline noise framework that connects chain-length growth to accumulated integrated-control-error variance, chain break probability (CBP), chain break fraction (CBF), and chain-strength scaling. We distinguish a moment-level uncorrelated ICE baseline, which yields a linear variance law, from a Gaussian closure that gives a closed-form erfc approximation for CBP. Experiments on the D-Wave Advantage2 Zephyr processor show that the calibrated baseline model captures the dominant growth trend of CBF with embedding size. However, the empirical critical chain-strength exponent ranges from
α=0.805 to
α=1.006 across chain-break tolerance thresholds, with 95% bootstrap confidence intervals consistently excluding the independent-noise prediction
α=0.5 ; a direct fit of a correlated-variance extension recovers
γ≈1.8 , consistent with the asymptotic relation
γ=2α . These results indicate that real-hardware variance accumulation deviates from the independent-noise reference and is consistent with a correlated component. The proposed framework offers quantitative guidance for embedding-aware chain-strength tuning and motivates more general noise models incorporating correlated and non-Gaussian hardware effects.