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IEEE Latin American Test Symposium (LATS)

Qubit-driven Fault Simulation

Vladimir I. Hahanov, Wajeb Gharibi, Eugenia I. Litvinova, Svetlana V. Chumachenko

Published Mar 1, 2019• 25 citations
Publisher

Abstract

Quantum data structures, methods, algorithms and software applications for parallel solution of combinatorial problems, including design and test, on classical computers by using extra memory are proposed. Quantum models and methods for design and test of specific logic functionalities are developed based on the use of vector qubit data structures and memory-driven architectures for parallel computing algorithms, in order to significantly improve the performance of testing and deductive simulation of digital systems-on-chips. A new quantum method of test generation for single stuck-at faults of logic functions through taking Boolean derivatives with respect to their qubit coverages is proposed. The quantum method of deductive simulation of stuck-at faults of logical functions through the synthesis of matrices of Boolean derivatives with respect to their qubit coverage has been developed. The performance of methods for test synthesis and their analysis has no analogues in algorithmic performance.

DOI
10.1109/latw.2019.8704583

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Quantum data structures, methods, algorithms and software applications for parallel solution of combinatorial problems, including design and test, on classical computers by using extra memory are proposed. Quantum models and methods for design and test of specific logic functionalities are developed based on the use of vector qubit data structures and memory-driven architectures for parallel computing algorithms, in order to significantly improve the performance of testing and deductive simulation of digital systems-on-chips. A new quantum method of test generation for single stuck-at faults of logic functions through taking Boolean derivatives with respect to their qubit coverages is proposed. The quantum method of deductive simulation of stuck-at faults of logical functions through the synthesis of matrices of Boolean derivatives with respect to their qubit coverage has been developed. The performance of methods for test synthesis and their analysis has no analogues in algorithmic performance.
An overview of the technologies of cyber-physical culture is proposed that is aimed at solving practical problems in the field of quantum parallel synthesis and analysis of digital systems based on qubit models and algorithms for design, testing, and simulation. Algorithms for deductive analysis of digital logic circuits leveraging qubit data structures, which significantly improve the processing performance of large scale digital systems are presented. Software and hardware solutions for the simulation of stuck-at faults based on the use of qubit vector descriptions of logic circuits are proposed. Algorithms for the synthesis of deductive expressions focused on fault simulation of x-functions, which are characterized by a high level of testability, are developed. Practical examples, proving the effectiveness of models, methods and algorithms for processing modern digital systems-on-chips, are described.
Context. It is known that data structures are decisive for the creation of efficient parallel algorithms and high-performance computing devices. Therefore, the development of mathematically perfect and technologically simple data structures takes about 80 percent of the design time, when about 20 percent of time and material resources are spent on algorithms and their hardware-software coding. This lead to search for such primitives of data structures that will significantly simplify the parallel high-performance algorithms which are working on them. Models and methods for testing and simulation of digital systems are proposed, which containing certain advantages of quantum computing in terms of implementation of vector qubit data structures in technology of classical computational processes. Objective. The goal of the work is development of an innovative technology for qubit-vector synthesis and deductive analysis of tests for their verification based on vector data structures that greatly simplify algorithms that can be embedded as BIST components in digital systems on chips. Method. The deductive faults simulation is used to obtain analytical expressions focused on transporting fault lists through a functional or logical element based on the xor-operation, which serves as a measure of similarity-difference between a test, a function and faults which is specified in the same way in one of the formats − a table, graph, equation. A binary vector is proposed as the most technologically advanced primitive of data structures for setting logical functionality for the purpose of parallel synthesis and analysis of digital systems. The parallelism of solving combinatorial problems is a physical property of quantum computing, which in classical computing, for parallel simulation and faults diagnostics, is provided by unitary-coded data structures due to excess memory. Results. 1) A method of analytical synthesis of deductive logic for functional elements on the gate level and register transfer level has been developed. 2) A deductive processor for faults simulation based on transporting input lists or faults vectors to external outputs of digital circuits was proposed. 3) The qubit-vector form of logic setting and methods of qubit synthesis of deductive equations for faults simulation were described. 4) A qubit-vector method for the tests’ synthesis which is using derivatives calculated by vector coverage of logic has been developed. 5) Models and methods verification is performed on test examples in the software implementation of structures and algorithms. Conclusions. The scientific novelty lies in the new paradigm of the technology for the synthesis of deductive RTL logic based on metric test equation, which forms the. A vector form for structures description is introduced, which makes it possible to apply wellknown technologies for the synthesis and analysis of logical circuits tests to effectively solve the problems of graph structures testing and state machine models of digital devices. The practical significance is reflected in the examples of analytical synthesis of deductive logic for functional elements on gate level and register transfer level. A deductive processor for faults simulation which is focused on implementation as a BIST tool, which is used in online testing, simulation and fault diagnosis for digital systems on chips is proposed. A qubit-vector form of the digital systems description is proposed, which surpasses the existing methods of computing devices development in terms of the metric: manufacturability, compactness, speed and quality. A software application has been developed that implements the main testing, simulation and diagnostics services which are used in the educational process to study the advantages of qubit-vector data structures and algorithms. The computational complexity of synthesis processes and deductive formulas for logic and their usage in fault simulation are given.
Quantum memory-driven computing on the classical computers for design and test of black-box functionality is considered. A method for synthesis and minimization test for the black-box functionality, based on a qubit derivative matrix and sequencer for searching a quasi-optimum coverage, is proposed. Examples of quantum memory-driven design and test minimization of the Schneider logic circuit are presented. An architecture and algorithm for parallel search of a quasi-minimal set of test vectors based on the logical structure is developed. The technological advantages of the qubit coverage leverage for increasing the speed of performance due to the parallel solution of the test synthesis and analysis for single stuck-at-faults of external and internal variables are shown.
Matrix method for quantum diagnosing functional failures and stuck-at faults in software or hardware units is proposed. It is based on qubit data structures comprising diagnostic information, which allows significantly reducing the computational complexity of the simulation and diagnosis due to the introduction of parallel logical operations on the matrix data. The quantum method for fault-free simulating digital units with the possibility of online repair of digital system components is presented. It is characterized by significantly improved performance due to addressed processing procedure of the functional primitives, defined by Q-coverages.
Cyberculture of quantum memory-driven computing integrates emerging technologies of parallel solution for time-consuming combinatorial problems. A scalable map of research relevant to quantum cyberculture is aimed at creating parallel algorithms for SoC Design and Test. The memory-driven innovation architecture of quantum computing is presented, which is defined by the leverage of photon read-write transactions on the structure of electrons in the absence of logic, associated with superposition and entanglement. A class of logical X-functions and their qubit models is introduced, that are technologically feasible for test, diagnosis, and fault simulation of SoC components. The architecture of services for design, test and verification of digital devices based on qubit models of logical primitives is described. A service for fault-free circuits simulation based on the qubit coverage of functional primitives is given. The models, cubit data structures and methods are focused and simulated on the classical computers by leveraging unitary coding binary states.
Memory-driven computing for the design and test of digital devices is considered. One of the possible solutions to the problem of design and test theory and methods of quantum memory-driven computing on the classical computers for their subsequent application in all fields of human activity is proposed. Engineering-focused definitions of computing types are presented, including quantum one, which leverages the superposition and entanglement notions, and also memory-driven computing. The necessity of joint and parallel solving the problem of the creation of a market-accessible quantum computer and development of quantum-focused applications and cloud services is explained. Examples of quantum memory-driven design and test of digital circuit fragments are presented. A method for synthesis and minimization test for the black-box functionality, based on a qubit derivative matrix and sequencer for searching a quasioptimum coverage, is proposed.