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IEEE Transactions on Circuits & Systems II Express Briefs

SPAD-Based Quantum Random Number Generator With an $N^{\rm{th}}$ -Order Rank Algorithm on FPGA

Alessandro Tontini, Leonardo Gasparini, Nicola Massari, Roberto Passerone

Published Apr 3, 2019• 9 citations
Publisher

Abstract

We present a compact, all-solid-state, low-cost quantum random number generator (QRNG) based on a single-photon avalanche diode (SPAD) and a field programmable gate array (FPGA). A new algorithm for random bit generation is described, ranking the inter-arrival times of a group of M photons detected by the SPAD device, and processed directly on the FPGA. The proposed approach improves the efficiency of generated random bits per detected photon, spanning from 0.5 bits/photon in case of 0 order rank, up to 0.875 bits/photon for second order rank. By extending the algorithm to higher orders, the proposed system approaches the maximum theoretical value of 1.0 bit/photon. The rate of generation of random numbers is limited by the SPAD minimum deadtime, achieving an experimentally proven bit rate of 7.3 Mbps. The standard randomness statistical tests are passed for a wide range of photon fluxes and for all the implemented rank orders with no additional post-processing on the generated sequence.

DOI
10.1109/tcsii.2019.2909013

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SPAD-Based Quantum Random Number Generator With an NthN^{\rm{th}}Nth -Order Rank Algorithm on FPGA
We present a compact, all-solid-state, low-cost quantum random number generator (QRNG) based on a single-photon avalanche diode (SPAD) and a field programmable gate array (FPGA). A new algorithm for random bit generation is described, ranking the inter-arrival times of a group of M photons detected by the SPAD device, and processed directly on the FPGA. The proposed approach improves the efficiency of generated random bits per detected photon, spanning from 0.5 bits/photon in case of 0 order rank, up to 0.875 bits/photon for second order rank. By extending the algorithm to higher orders, the proposed system approaches the maximum theoretical value of 1.0 bit/photon. The rate of generation of random numbers is limited by the SPAD minimum deadtime, achieving an experimentally proven bit rate of 7.3 Mbps. The standard randomness statistical tests are passed for a wide range of photon fluxes and for all the implemented rank orders with no additional post-processing on the generated sequence.
Experimental demonstration of a quantum random number generator based on one single-photon avalanche diode (SPAD) detector, a T / ( T − t ) pulse-shaped laser, and an field-programmable gate array (FPGA) acquisition module is presented. An integrated laser driver drives an external laser diode at 670 nm wavelength, whereas the SPAD with a photon detection probability of 18.5% is integrated together with an active quenching-resetting circuit. The SPAD detector generates counts for the interarrival time (IAT) measurement system implemented in an FPGA, where the change of the IATs between consecutive pulses is used to derive a random bit stream. It is shown how the application of a pulse-shaped laser driver can increase the performance of the system as compared to the continuous-wave operation of the laser diode to achieve the maximum generation rate of 5 Mbps while using a single SPAD. The generated numbers pass all randomness tests of the National Institute of Standards and Technology (NIST), Dieharder, and ENT test (pseudorandom number sequence test) suits.
A quantum random generator based on photon detection is here presented. The system consists of a photon source, typically a commercial LED, coupled with a detector with single photon detection capability. The detector is composed of a Single-Photon Avalanche Diode (SPAD) and a time stamp circuit, which samples the arrival time of impinging photons within a predefined temporal window. The proposed implementation optimizes the area, allowing embedding all circuitry into a single pixel, and increases the efficiency of random bit extraction. Moreover, the adopted fast pre-charge mode of the SPAD quenching circuit reduces the afterpulsing probability, and hence possible undesirable correlation in the resulting random bit sequence. Thanks to the implemented random bit extraction, experimental results show that the pixel has a flat behavior for a significant range of light intensity, which makes the pixel robust against variations of external PVT parameters. The maximum achievable bit rate has been measured equal to 1 Mbps, while random sequences are shown to pass NIST tests without any post-processing.
A 16×1616\times 1616×16 Pixel Post-Processing Free Quantum Random Number Generator Based on SPADs
In this brief, we present a 16 × 16-pixel quantum random number generator (QRNG) based on Single-Photon Avalanche Diodes, implemented in CMOS 150-nm technology. Each pixel consists of two detectors, featuring 17.2 μm ×7.7 μm size, and an arbiter, based on a phase comparator, enhancing the working range of the generator. The QRNG has achieved a random bit efficiency of 90% at a given observation window of 200 ns. The maximum speed is up to 18.2 Mbps for the whole array due to limited readout capability. The measurement result shows the random numbers can pass the standard randomness test without any post-processing.
A compact quantum random number generator (QRNG) based on an array of Single Photon Avalanche Diodes (SPADs) is presented here. The main feature of the proposed chip is the capability to generate random numbers without the use of any external source of light. In this view, SPADs are configured to be used in two ways: 1) as a controlled light emitter and 2) as a detector. An embedded logic is able to distinguish dark events against detected emitted photon in such a way to make the system sensitive only to the presence of light. The extracted random bits show a uniform distribution and the QRNG, thanks to an integrated conditioning block maximizing the output entropy, eventually passes all AIS31 tests. The average raw bit rate in the default device configuration (one enabled column) is measured equal to 800 kbps.
A random number generation approach comprising a silicon nanocrystals LED (Si-NCs LED), silicon single photon avalanche photodiode (Si SPAD) and a field-programmable gate array (FPGA) is introduced. The Si-NCs LED is the source of entropy with photon emission in the visible range detectable by silicon detectors allowing the fabrication of an all-silicon-based device. The proposed quantum random number generator (QRNG) is robust against variations of the internal and external parameters such as aging of the components, changing temperature, the ambient interferences and the silicon detector artifacts. The raw data show high quality of randomness and passed all the statistical tests in National Institute of Standards and Technology (NIST) tests suite without the application of a post-processing algorithm. The efficiency of random number generation is 4-bits per detected photon.
For globally connected devices like smart phones, personal computers and Internet-of-things devices, the ability to generate random numbers is essential for execution of cryptographic protocols responsible for information security. Generally, a random number generator should be small, robust, utilize as few hardware and energy resources as possible, yet provide excellent randomness at a high enough speed (bitrate) for a given purpose. In this work we present a quantum random number generator (QRNG) which makes use of a photoelectric effect in single-photon avalanche diodes (SPADs) as a source of randomness and is scalable to any desired bitrate. We use the random flip-flop method in which random bits are obtained by periodic sampling of a randomly toggling flip-flop. For the first time we investigate this method in detail and find that, out of two main imperfections, bias is due only to hardware imperfections while autocorrelation predominantly resides with the method itself. SPADs are integrated on a silicon chip together with passive quenching and digital pulse-shaping circuitry, using a standard 180 nm CMOS process. A separate FPGA chip derives random numbers from the detection signals. The basic QRNG cell, made of only two SPADs and a few logic circuits, can generate up to 20 Mbit/s that pass NIST statistical tests without any further postprocessing. This technology allows integration of a QRNG on a single silicon chip using readily available industrial processes.