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IEEE Transactions on Applied Superconductivity

Clockless Dynamic SFQ and Gate With High Input Skew Tolerance

Sergey V. Rylov

Published Jan 30, 2019• 44 citations
Publisher

Abstract

We have introduced a new class of dc-powered Single Flux Quantum (SFQ) logic that uses dynamic (self-resetting) internal states to achieve completely clock-free gate operation and provide high immunity to input data skew. We call it DSFQ (dynamic SFQ) logic. We have successfully designed and tested a 2-input DSFQ and gate and showed its ability to hold dynamically its internal states for over 25 ps while operating at 10 GHz clock frequency. We also demonstrated picosecond-scale dynamics of DSFQ circuit with an on-chip Josephson sampler, with only low-speed interfaces required.

DOI
10.1109/tasc.2019.2896137

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We have introduced a new class of dc-powered Single Flux Quantum (SFQ) logic that uses dynamic (self-resetting) internal states to achieve completely clock-free gate operation and provide high immunity to input data skew. We call it DSFQ (dynamic SFQ) logic. We have successfully designed and tested a 2-input DSFQ and gate and showed its ability to hold dynamically its internal states for over 25 ps while operating at 10 GHz clock frequency. We also demonstrated picosecond-scale dynamics of DSFQ circuit with an on-chip Josephson sampler, with only low-speed interfaces required.
In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.
In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.
We propose an asynchronous single flux quantum (SFQ) logic gate composed of a conventional clocked logic gate and an input signal merger that generates a self-clock for the clocked logic gate. By using this self-clocking, we can design any 0-preserving logic gate, including exclusive OR (XOR). The proposed asynchronous SFQ logic gates have adjustable allowable input skew by varying the delay between the merger and internal clock input for the clocked logic gate. We design and evaluate the asynchronous AND, OR, and XOR gates that have an allowable input skew of approximately 8 ps assuming the use of the 10 kA/cm2Nb fabrication process using the proposed design method. We experimentally confirm the correct operation of the asynchronous SFQ XOR gate. We design a completely asynchronous 4-bit-input carry-lookahead adder (CLA) using the designed asynchronous gates. We found that the circuit area and number of Josephson junctions required to design a 4-bit-input CLA can be reduced by > 50% compared to that of the synchronous concurrent-flow 4-bit-input CLA without deterioration of the throughput.
Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>
Novel reconfigurable superconductive single flux quantum (SFQ) logic devices, the functions of which can be dynamically reconfigured by inputting control signals, have been investigated. The characteristics of single flux quantum circuits can be easily modulated by applying currents or magnetic fields because of the high sensitivity of superconductive circuits. We investigated several design approaches for the realization of dynamically reconfigurable SFQ logic devices. We employed direct current injection to the logic gate using a non-destructive read-out flip-flop. By changing the internal state of the non-destructive read-out flip-flop, the logic function can be dynamically reconfigured. We have designed and tested a dynamically reconfigurable Josephson transmission line (JTL)/delay flip-flop (DFF) circuit. The measured dc bias margin was 72.5-107.2%. Furthermore, we have demonstrated the operation of a variable bit-length shift register, composed of the dynamically reconfigurable JTL/DFF circuits. The investigated design approach can be applied to more sophisticated dynamically reconfigurable single flux quantum logic gates.