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International Conference on Information Technology in Medicine and Education

Look-Up-Table Decoding and Architecture Optimization for Scale-Min-Sum Polar Decoders

Xiumin Wang, Rui Gu, Jun Li, Haiyan Cao, Zhengquan Li

Published Oct 1, 2018• 0 citations
Publisher

Abstract

As to realize believe propagation (BP) for polar decoding, the scaled min-sum (SMS) algorithm is widely used in hardware realization for polar decoders. However, the decoding performance of SMS algorithm is still not good as the length of polar codes increase, and its computing architecture,which called processing elements (PE) needs to be further optimized due to its long critical path. In this paper, referring to the method used in LDPC/Turbo decoding, a look-up-table (LUT) algorithm and its modified version called LUT-SMS are proposed for polar decoding. The simulation result shows that, compared with the SMS algorithm, the proposed LUT-SMS algorithm can lead to 0.3 dB extra decoding gain when the code length up to 2048. For a different trade-off, a new SMS computing architecture which has shorter computing path is proposed to solve the long delay of the polar decoders. The hardware implementation result shows that, the optimized SMS computing architecture can also achieve more than 32% increase in throughput for the case of (256,128) polar decoder without much extra hardware consumption. As a result, both these two optimization schemes have good promotion for polar decoding.

DOI
10.1109/itme.2018.00189

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Low-Density Parity check (LDPC) codes offer high-performance error correction near the Shannon limit which employs large code lengths and some iterations in the decoding process. The conventional decoding algorithm of LDPC is the Log Likelihood Ratio based Belief Propagation (LLR BP) which is also known as the `Sum-Product algorithm' which gives the best decoding performance and requires the most computational complexity and implementations with increased hardware complexity. Another simpler variant of this algorithm is used which is known as `min-sum algorithm' which reduces computational complexity as well as hardware complexity but with reduced accuracy. This paper analyzes the reason min-sum algorithm is more prone to errors when compared to the sum-product algorithm, and puts forward two improved algorithms which improve the performance of the min-sum algorithm with comparable algorithmic complexity.
Belief propagation (BP) decoding of polar codes benefits from the high parallelism in hardware implementation and consequently provides high throughput compared to successive cancellation-based decoding algorithms. As the evolved log-likelihood ratios (LLRs) in the decoding process have a wide dynamic range, the quantization error can degrade the error correction performance of the BP decoder. To reduce the quantization error in a uniform quantization scheme, we may need to use more bits for each LLR value which is not desirable due to the required memory space. In this paper, we design an efficient hardware architecture for non-uniformly quantized LLR messages in BP decoding where the arithmetic operations on logarithmically compressed messages are replaced with the mapping to precomputed results in lookup tables. By employing 5-bit non-uniform quantization, the designed BP decoder architecture reduces the required memory space by 37.5 percent compared to 8-bit uniform quantization while additionally improving the block error rate (BLER) by more than 0.1 dB in high SNR regimes. Compared to uniform quantization, the BLER improvement of the designed architecture is up to 0.4 dB when both quantization schemes use 5 bits for LLRs.
In this paper, we propose low complexity implementations of sum-product algorithm (SPA) for decoding low-density parity-check (LDPC) codes. The finite precision implementations for SPA have an important tradeoff between the decoding performance and hardware complexity caused by two dominant area consuming factors. One is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of nonlinear function Psi(x). The proposed two types of variable quantization schemes result in significant reductions of LUT sizes. Computer simulation results indicate that the performance losses of SPA with reduced LUT by proposed schemes are less than 0.05 dB compared to that of SPA with original LUT. Moreover, the proposed implementation offers a large reduction in the finite wordlength for storage of updated messages using a kind of compression technique without performance losses. As a result, using the proposed implementation based on variable quantization scheme and data compression technique, the novel proposed implementation for SPA decoder architecture offers significant reductions of 75% and 33% in hardware complexities of LUT and memories, respectively, without significant performance degradations over conventional uniform quantization scheme. Furthermore, since each LUT with variable (6:3) quantization scheme II has only 8 entries, its hardware implementation can be replaced with a small combination circuit instead of readonly-memory (ROM) for LUT