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International Conference on Wireless Communications and Signal Processing (WCSP)

A Distributed CRC Early Termination Scheme for High Throughput QC-LDPC Codes

Hao Wu, Fang Wang, Yuqing Yuan

Published Oct 1, 2018• 5 citations
Publisher

Abstract

In order to avoid unnecessary computation and increase system throughput, various early termination schemes are adopted in quasi-cyclic low-density parity-check (QC-LDPC) decoders. Cyclic redundancy check (CRC) based early termination scheme can be used when the information bits are concatenated with the CRC. The CRC is usually checked at the end of an iteration to verify the integrity of information bits. The latency of the CRC calculation results in an unnecessary decoding process. In this paper, we propose a distributed CRC early termination scheme for high throughput QC-LDPC codes. The proposed scheme distributes the CRC calculation in each layer of the iteration to minimize unnecessary computation and increase system throughput.

DOI
10.1109/wcsp.2018.8555687

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In order to avoid unnecessary computation and increase system throughput, various early termination schemes are adopted in quasi-cyclic low-density parity-check (QC-LDPC) decoders. Cyclic redundancy check (CRC) based early termination scheme can be used when the information bits are concatenated with the CRC. The CRC is usually checked at the end of an iteration to verify the integrity of information bits. The latency of the CRC calculation results in an unnecessary decoding process. In this paper, we propose a distributed CRC early termination scheme for high throughput QC-LDPC codes. The proposed scheme distributes the CRC calculation in each layer of the iteration to minimize unnecessary computation and increase system throughput.
In modern communication systems, the concatenation of a low-density parity-check (LDPC) code with a cyclic redundancy check (CRC) code is commonly used for error correction. In this paper, we propose a low-complexity two-stage scheme for decoding these codes using their concatenation structures. In the first stage, the traditional belief propagation (BP)-based iterative algorithm with a relative small maximum number of iterations is performed for decoding the LDPC code. If an LDPC codeword is obtained in this stage, the decoding process terminates. Otherwise, the second stage of the decoding process is performed, in which the guessing random additive noise decoding (GRAND) algorithm is applied to the CRC code. A list of information sequences satisfying the CRC check is obtained, each of which is then encoded to an LDPC codeword. The most likely codeword among them is the output of the decoding approach. The simulation results indicate that the proposed two-stage decoding approach can outperform the traditional BP-based iterative algorithm with a large maximum number of iterations. Moreover, the average complexity of the proposed approach is relatively low.
According to its excellent error recovery capability, Low Density Parity Check code has been adopted as a channel coding method for 5G NR data channels. This paper proposes a novel early termination scheme of the layered quasi-cyclic LDPC code decoder for a 5G NR data channel. In terms of early termination and error correction performance, the proposed scheme shows improved performance compared to the conventional scheme. Simulation results show that 18.7% reduction with regard to average iteration numbers can be achieved compared to the traditional termination schemes, such as syndrome check(SDC) and hard decision aid(HDS). Furthermore, the proposed scheme shows error correction performance improvement of 0.2dB.
Low-density parity-check (LDPC) codes are one of the most popular linear block codes have ever been used in the communication system.The standard two-phase message passing decoding (TPMPD) algorithm and the layered message-passing decoding (LMPD) algorithm are widely used in LDPC decoder.However, the convergence speed of LMPD algorithm is much faster than that of TPMPD algorithm, particularly in the condition of high signal noise ratio (SNR).In this paper, we propose an early termination criterion for quasi-cyclic low-density parity-check (QC-LDPC) codes based on LMPD algorithm with fast convergence speed.The strategy is to dynamically reprocesses the uncorrected related layers while skipping the corrected ones.Simulations show that 3% reduction in terms of iteration numbers can be achieved with no performance loss compared to the traditional termination strategies, such as hard decision aided (HDA) strategy and parity check equations (PCE) strategy.Furthermore, the optimized early termination strategy achieves low complexity in hardware implementation.
This paper presents a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes which is devised based on the section-wise cyclic structure of their parity-check matrices. The decoding scheme significantly reduces the hardware implementation complexity of a QC-LDPC code decoder in terms of the number of message processing units and the number of wires required to connect the message processing units. A long high-rate high-performance QC-LDPC code is used to demonstrate the effectiveness of the proposed decoding scheme. Using this long code as the mother code, descendant QC-LDPC codes of various lengths and rates can be constructed by puncturing and masking the columns and rows of the parity-check matrix of the mother code. These descendant codes can be decoded by deactivating specific sets of message processing units of the mother decoder.
In this paper, the authors propose an efficient highly-parallel decoder architecture using partially overlapped decoding scheme for quasi-cyclic (QC) low-density parity-check (LDPC) codes, which leads to reduction in hardware complexity and power consumption. Generally, due to the regularly structured parity-check matrix H of QC LDPC codes, the message updating computations in the check node unit (CNU) and the variable node unit (VNU) can be efficiently overlapped, which increases the decoding throughput by maximizing the hardware utilization efficiency (HUE). However, the partially overlapped decoding scheme cannot be used to design a highly-parallel decoding architecture for high-throughput applications. For (3, 5)-regular QC LDPC codes, our proposed method could reduce the hardware complexity by approximately 33% for the CNU and 20% for the VNU in the highly-parallel decoder architecture without any performance degradation. In addition, the power consumption can be minimized by reducing the total number of memory accesses for updated messages.
In conventional satellite broadcasting systems,e.g.DVB-S2,the error-correction schemes are often based on the concatenation of BCH and low-density parity-check(LDPC) codes,so as to obtain excellent bit error rate(BER) performance.As the inner codes,LDPC codes are traditionally decoded by iterative algorithms with many iteration cycles.In virtue of the concatenated structure of BCH and LDPC codes,a novel iterative decoding structure involving the embedment of BCH error-check function into each iterative cycle of LDPC is proposed.Computer simulations show that the iteration number of LDPC decoding with the proposed algorithm is obviously smaller than with traditional algorithm,thus greatly lowering the additional complexity of BCH error-check codes.Therefore,the total complexity and latency of the iterative decoding could be sufficiently reduced,while the similar system BER performance is maintained.