A high-fidelity memory scheme for quantum data buses

Yong Hui Yu

Boyang Liu, Wei Cui, Hong‐Yi Dai +2 more

A novel quantum memory scheme is proposed for quantum data buses in scalable quantum computers by using adjustable interaction. Our investigation focuses on a hybrid quantum system including coupled flux qubits and a nitrogen–vacancy center ensemble. In our scheme, the transmission and storage (retrieval) of quantum state are performed in two separated steps, which can be controlled by adjusting the coupling strength between the computing unit and the quantum memory. The scheme can be used not only to reduce the time of quantum state transmission, but also to increase the robustness of the system with respect to detuning caused by magnetic noises. In comparison with the previous memory scheme, about 80% of the transmission time is saved. Moreover, it is exemplified that in our scheme the fidelity could achieve 0.99 even when there exists detuning, while the one in the previous scheme is 0.75.

Nadia Nedjah, Luiza de Macedo Mourelle

This chapter discusses the overall hardware architecture of a quantum processor. Emulation of quantum processing requires primarily an efficient way to store and retrieve quantum information. The quantum processor employs different purpose memories. The proposed co-processor implements a quantum machine capable of performing certain quantum operations on a set of q-bits that form the machine quantum state. It is an isolated system that interacts with a host processor through communication channels. The main processor sends properly formatted commands that invoke quantum operations on q-bits, to manipulate the quantum state. The channel configuration is used because it considers the sequential characteristic of a quantum algorithm due to the potential dependence of the result of the previous operation on one or more q-bits. The full-duplex configuration would also be possible, given the required control related to data dependency. The interaction between the units and memories that compose the co-processor is done via data buses, address buses and/or control buses.

Zhiqiang Zhang, Ravi Kumar, Mathias Alexander Seidler +3 more

Viacheslav V. Kuzmin, Pietro Silvi

We propose a variational quantum algorithm to prepare ground states of 1D lattice quantum Hamiltonians specifically tailored for programmable quantum devices where interactions among qubits are mediated by Quantum Data Buses (QDB). For trapped ions with the axial Center-Of-Mass (COM) vibrational mode as single QDB, our scheme uses resonant sideband optical pulses as resource operations, which are potentially faster than off-resonant couplings and thus less prone to decoherence. The disentangling of the QDB from the qubits by the end of the state preparation comes as a byproduct of the variational optimization. We numerically simulate the ground state preparation for the Su-Schrieffer-Heeger model in ions and show that our strategy is scalable while being tolerant to finite temperatures of the COM mode.

Matteo Bergonzoni, Laura Pecorari, Sam Norrell +3 more

Efficient quantum error correction and fault-tolerant quantum computing require scalable, high-fidelity long-range connectivity. In neutral-atom quantum computers, this is commonly achieved through atom transport, but shuttling introduces latency and motional heating that worsen with system size. Here, we introduce a neutral-atom architecture based on static atomic buses, in which auxiliary mediator atoms enable long-range entangling operations without qubit transport. The architecture naturally supports long-range stabilizer measurements in high-rate LDPC codes and transversal logical gates between neighboring surface-code patches, enabling a modular framework for efficient logical memories, Clifford computation, and magic-state distillation. To realize these capabilities, we co-design optimal-control protocols for bus-mediated controlled-Z gates that incorporate both microscopic neutral-atom dynamics and architectural constraints. We obtain smooth bus-mediated gates with fidelities approaching 99.9% and durations of a few hundred nanoseconds by combining time-optimal control with interaction-flatness and robustness constraints. Large-scale simulations of quantum error correction and logical entangling operations between neighboring surface-code patches predict more than an order-of-magnitude improvement in logical error rates compared with atom-shuttling architectures under realistic noise. The architecture achieves logical gate times of approximately 100 us and quantum-error-correction cycle times of about 1 ms for code distances d<12. These results establish static atomic buses as a practical alternative to atom shuttling for scalable fault-tolerant neutral-atom quantum computing.