In this research work, the transistor level implementation and QCA implementation of TR reversible gate are performed and a comparison between both techniques on the ground of Area is executed. In the later section, a new-fangled design of the reversible adder and subtractor RSG gate is presented. This novel architecture can perform addition and subtraction operation simultaneously, which was never performed before using any of the existing reversible circuits. The proposed novel reversible gate, which uses 2X2 quantum gates and has a quantum cost of five, can be operated as Reversible Half Adder as well as Half Subtractor concurrently. The reversible gate proposed in this research will find numerous applicability in several DSP applications where half adder and half subtractor operates simultaneously.
In this research work, the transistor level implementation and QCA implementation of TR reversible gate are performed and a comparison between both techniques on the ground of Area is executed. In the later section, a new-fangled design of the reversible adder and subtractor RSG gate is presented. This novel architecture can perform addition and subtraction operation simultaneously, which was never performed before using any of the existing reversible circuits. The proposed novel reversible gate, which uses 2X2 quantum gates and has a quantum cost of five, can be operated as Reversible Half Adder as well as Half Subtractor concurrently. The reversible gate proposed in this research will find numerous applicability in several DSP applications where half adder and half subtractor operates simultaneously.
In [1] we have presented the reversible subtractor designs based on a new reversible TR gate (TR refers to Thapliyal Ranganathan). In [1] as the quantum gates implementation of the TR gate was not known, only the upper bound on the quantum cost of the reversible subtractors units were established. In this work, we present a new design of the reversible half subtractor based on the quantum gates implementation of the reversible TR gate. The reversible TR gate is designed from 2×2 quantum gates such as CNOT and Controlled-V and Controlled-V+gates. The design of the proposed reversible half subtractor is shown to be better than the design presented in [2], [1] in terms of the quantum cost and delay while maintaining the minimum number of garbage outputs. Further, we present a new design of the reversible full subtractor based on the proposed quantum gates implementation of the TR gate. The proposed reversible full subtractor is optimized in terms of quantum cost, delay and garbage outputs by utilizing the identity property of V and V+reversible gates. The proposed reversible full subtractor is shown to be better than the existing design reported in [3], [1]. The reversible subtractors proposed in this work will be useful in a number of digital signal processing applications.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
The futuristic computing is desired to be more power full with low-power consumption.That is why quantum computing has been a key area of research for quite some time and is getting more and more attention.Quantum logic being reversible, a significant amount of contributions has been reported on reversible logic in recent times.Reversible circuits are essential parts of quantum computers, and hence their designs are of great importance.In this paper, designs of reversible circuits are proposed using a recently proposed reversible gate for arithmetic and logic operations to implement various micro-operations (simple add and subtract, add with carry, subtract with borrow, transfer, incrementing, decrementing etc., and logic operations like XOR, XNOR, complementing etc.) in a reversible computer like quantum computer.The two new reversible designs proposed here for half adder and full adders are also used in the presented reversible circuits to implement various microoperations.The quantum costs of these designs are comparable.Many of the implemented micro-operations are not seen in previous literatures.The performances of the proposed circuits are compared with existing designs wherever available.
Quantum processors are a central element of a quantum computer. Processors are responsible for performing the fundamental operations like addition, subtraction, etc. of any computer. This also involves the arithmetic unit and has a different configuration for the quantum computer than for a classical computer. Multiplication is essentially repeated addition and division is repeated subtraction. But for quantum computer other methodologies have to be used for arithmetic. In this paper a Quantum Full Adder/Subtractor Circuit, using the reversible Peres Gate, R3Gate and a NOT Gate, is proposed. So, the proposed design can be used for both modes, adder and subtractor on quantum operation. The authors have also compared proposed design with other designs reported, in terms of Gate count, Garbage bits, Quantum cost and Delay. The authors have achieved a 62.5% increment in delay and a low power computing reversible logic in which the computation is faster and energy efficient. Using IBM Qiskit, the authors have created and tested the circuit.
The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.
This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU).