We developed a general framework for synthesizing target gates by using a finite set of basic gates, which is a crucial step in quantum compilation. When approximating a gate in SU(
n), a naive brute-force search requires a computational complexity of
O(1/ε(n2−1)) to achieve an approximation with error
ε. In contrast, by using our method, the complexity can be reduced to
O(−n2logε/ε((n2−1)/2)). This method requires almost no assumptions and can be applied to a variety of gate sets, including Clifford+
T and Clifford+
V. Further, we introduce a suboptimal but short run-time algorithm for synthesizing multi-qubit controlled gates. This approach highlights the role of subgroup structures in reducing synthesis complexity and opens a new direction of study on the compilation of multi-qubit gates. The framework is broadly applicable to different universal gate sets, and our analysis suggests that it can serve as a foundation for resource-efficient quantum compilation in near-term architectures.
We present Limbo, a quantum multi-chip-first compiler that combines graph-partitioning and routing-first approaches to compilation. On a 24-cell benchmark against TKET, Limbo outperforms in every cell. On the hardest cell, it reduces cross-chip 2-qubit operations by 78% and compile time by a factor of 2735; the median compile-time ratio across the matrix is 119. Under a calibrated noise model whose intra-chip and cross-chip error rates draw from published experimental characterizations, Limbo's output reaches higher Hellinger fidelity than TKET on every informative cell. The pipeline first analyzes the structural topology of the input interaction graph and selects a matching cloud vendor. It then partitions the qubits across chips using multi-level hypergraph partitioning, sequences the residual cross-chip operations through an event scheduler driven by topological sorting, and transpiles each per-chip sub-circuit against the chosen device's coupling map and native gate set. In testing, we executed the pipeline end-to-end on Rigetti's Cepheus superconducting QPU and exercised the noise-aware routing path against the device's live qubit calibration data. Direct hardware validation of the multi-chip architectural claim itself remains, at this moment, gated on publicly cloud-accessible multi-chip quantum hardware. The open-source SDK is available at github.com/Jminding/Limbo-Quantum, with the compiler API (planned to be released in Fall 2026), project information, and the full benchmark matrix at limbosys.dev.
In recent years, small-scale quantum information processors have been realized in multiple physical architectures. These systems provide a universal set of gates that allow one to implement any given unitary operation. The decomposition of a particular algorithm into a sequence of these available gates is not unique. Thus, the fidelity of the implementation of an algorithm can be increased by choosing an optimized decomposition into available gates. Here, we present a method to find such a decomposition, where a small-scale ion trap quantum information processor is used as an example. We demonstrate a numerical optimization protocol that minimizes the number of required multi-qubit entangling gates by design. Furthermore, we adapt the method for state preparation, and quantum algorithms including in-sequence measurements.