Next generation of quantum computers calls for reduced dc power dissipation of the cryogenic low‐noise amplifier (LNA) applied in reading out the superconducting qubits. This article reports on processing and evaluation of a 100‐nm gate length indium phosphide high electron mobility transistor (InP HEMT) technology used in the design of such LNAs. InP HEMTs with size of 4 × 50 µm were measured on‐wafer by DC and S‐parameter characterization. Device noise performance was indirectly evaluated by measuring and modeling the gain and noise of a three‐stage hybrid 4–8 GHz cryogenic LNA equipped with the InP HEMTs. When operating the LNA at a DC power of 2.1 mW, the InP HEMT LNA average noise temperature was 1.4 K with an average gain of 41.6 dB. The minimum noise temperature of the InP HEMT was estimated to be 1.1 K at 6 GHz. The performance achieved for the InP HEMT LNA is comparable to the LNAs currently used in quantum computing while requiring only 27% of the DC power consumption. Small‐signal modeling of the InP HEMT suggested that this was due to a low output conductance associated with a large gate‐recess length used in device fabrication.
The connection of RSFQ circuits with commercial room temperature electronics and amplifying SFQ pulses with high data rates require cryogenic interface amplifiers. Such amplifiers should provide extremely high bandwidth, low noise and low power consumption at the same time. Various hybrid amplifiers based on commercial p-HEMT transistors in an embedded microwave design were designed and characterized. Towards the p-HEMT transistor characterization at cryogenic temperature the biasing settings according to an optimum between voltage gain and low power consumption were determined. Thus a total power consumption of 2 mW and a voltage gain of 12 dB per single stage were achieved. For a preamplifier and an amplifier concept a multiple number of these stages were implemented in a microstrip and a coplanar transmission line design with a special matched interconnect taper towards the RSFQ components. Measurements of the amplifiers, the combination of an amplifier with a RSFQ circuit at 4.2 K showed their good performances without any disturbance of the RSFQ circuit. Due to the losses between the stages a total gain of 25 dB with a four stage amplifier was achieved; pulse rates went up to 3 Gb/s. The total power consumption was in the range of 8 mW. Further increase of data rates will be achieved by improving the matching between RSFQ output stage and amplifier.
High-fidelity single-shot readout of superconducting qubits is essential for fault-tolerant quantum computation. Without a quantum-limited amplifier such as a Josephson parametric amplifier, the cryogenic high-electron-mobility-transistor (HEMT) low-noise amplifier (LNA) at the 4 K stage is the dominant noise source in the readout chain. HEMT LNAs are conventionally characterized by Y-factor measurements of the noise temperature
TN, independently of the quantum measurement they ultimately serve. Here we present a qubit-in-the-loop benchmarking method. The method uses the two-dimensional IQ histogram of single-shot readout as a direct figure of merit. We apply it to three state-of-the-art cryogenic InP HEMT LNAs with 53\%, 60\%, and 70\% channel indium content, together with a commercial reference amplifier. The 60\% and 70\% devices have similar
TN in Y-factor measurements, both lower than the 53\% device. The 70\% device has the highest gain, but qubit readout SNR and assignment fidelity
Fa instead peak at 60\%. Using this method, we map
Fa against HEMT LNA dc power consumption for each device.
Fa does not simply saturate with increasing power. For several devices it declines above a device-dependent power well below typical operating points. For the 60\% device, which has the highest overall
Fa, about 1~mW is needed to maintain
Fa>85%. Across all four devices,
Fa>80% is reached with as little as about 0.3~mW, roughly an order of magnitude below typical operating points. These results establish a qubit-referenced benchmarking methodology and provide practical guidance for amplifier selection and bias in power-constrained multi-qubit readout systems.