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Gaussian Random Number Generator Based on FPGA

Yue Hu, Yan Xiang Wu, Y. Chen, Guochun Wan

Published Feb 20, 2018• 2 citations
OpenAlex

Abstract

Based on the research of the current situation of continuous variables quantum cryptographic key QCK and in order to guarantee the effect of communication, we aim to build a quantum communication system based on Reverse Reconciliation Protocol. Thus, a good Gaussian Random Number Generator based on FPGA (Field Programmable Gate Array) is proposed in this paper which can run fast and acquire a high throughput per slice. In this paper, Gaussian random number generator is based on the analysis of Box-Muller algorithm. Besides, seeds for Gaussian random number are input by mechanical keyboard which joggles randomly. Implementation results on Altera FPGA show that the proposed hardware design could generate Gaussian random number with period of $2^{32}-1$. Finally, we get the mean values, variances, maximum deviations and distribution diagrams of the generated Gaussian random numbers(GRN) by importing these data into Matlab. To assess the quality of these generated GRN, we further compare them to these GRN generated by Matlab.

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Based on the research of the current situation of continuous variables quantum cryptographic key QCK and in order to guarantee the effect of communication, we aim to build a quantum communication system based on Reverse Reconciliation Protocol. Thus, a good Gaussian Random Number Generator based on FPGA (Field Programmable Gate Array) is proposed in this paper which can run fast and acquire a high throughput per slice. In this paper, Gaussian random number generator is based on the analysis of Box-Muller algorithm. Besides, seeds for Gaussian random number are input by mechanical keyboard which joggles randomly. Implementation results on Altera FPGA show that the proposed hardware design could generate Gaussian random number with period of 232−12^{32}-1232−1. Finally, we get the mean values, variances, maximum deviations and distribution diagrams of the generated Gaussian random numbers(GRN) by importing these data into Matlab. To assess the quality of these generated GRN, we further compare them to these GRN generated by Matlab.
Abstract Quantum key distribution is the process of using quantum communication to establish a shared key between two parties. It has been demonstrated the unconditional security and effective communication of quantum communication system can be guaranteed by an excellent Gaussian random number (GRN) generator with high speed and an extended random period. In this paper, we propose to construct the Gaussian random number generator by using field‐programmable gate array (FPGA), which is able to process large data in high speed. We also compare three algorithms of GRN generation: Box‐Muller algorithm, polarization decision algorithm, and central limit algorithm. We demonstrate that the polarization decision algorithm implemented in FPGA requires less computing resources and also produces a high‐quality GRN through the null hypothesis test.
The continuous-variable quantum key distribution experimental system requires the randomness and speed of a Gaussian modulator. We present the hardware design for a Gaussian random number (GRN) generator based on the Box–Muller method, which can be implemented on a field-programmable gate array (FPGA). An external high-speed true random number generator application-specific integrated circuit (ASIC) is used to this end. The ASIC operates faster and more independently compared with other Gaussian algorithms based on a linear feedback shift register. The trigonometric and logarithmic functions are calculated using the nonuniform piecewise linear approximation. The calculation of the Gaussian random modulus and phase value is realized using this hardware. Compared with an arbitrary waveform generator, the GRN can be uploaded to a computer to estimate the security key rate. Furthermore, the GRN generator accurately provides a Gaussian probability density function that passes the Jarque–Bera inspection and Lilliefors tests. The proposed FPGA-based system is demonstrated to convert eight-channel 320-Mbps uniform random numbers to 40-MHz 16-bit GRN in real time. Finally, the control of the optical module and Gaussian modulation is realized via the FPGA-based outputs of four dual-channel, 16-bit, 1-giga samples per second digital-to-analog converters.
In quantum cryptography, the Gaussian Random Number(GRN) plays a crucial role. The Box-Muller is exact method for generating Gaussian random numbers but it requires very complex arithmetic operations. The polarization decision method uses less arithmetic operations and less I/O pins. In this paper we have proposed novel floating point architecture to produce Gaussian random numbers(GRN). In this Floating point architecture initially a software approach is followed to obtain for Uniform Random Number(URN) and perform mathematical computation techniques to generate GRN, hence the overall architecture complexity is reduced when compared to fixed polarization decision method. The proposed floating point architecture achieves precision value 0.001 and 30% less in bonded IOBS which results in simplification of routing and enhance the timing performance. The design is implemented and performed using Xilinx on ZC706 FPGA.
The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.
Most hardware "true" random number generators (TRNGs) take advantage of the thermal agitation around a flip-flop metastable state. In field programmable gate arrays (FPGAs), the classical TRNG structure uses two clocks, either from a PLL or from ring oscillators, in order to sample one by the other. This creates good TRNGs albeit limited in frequency by the interference rate which cannot exceed a few Mbit/s. This article presents an architecture allowing higher bit rates while maintaining provable unconditional security. This requirement becomes stringent for secure communication applications such as the cryptographic quantum key distribution (QKD) protocols. The proposed architecture is very simple as it is based on an open loop structure without any specific component such as PLLs.
Random number generators (RNG) are an important resource in many areas: cryptography (both quantum and classical), probabilistic computation (Monte Carlo methods), numerical simulations, industrial testing and labeling, hazard games, scientific research, etc. Because today's computers are deterministic, they can not create random numbers unless complemented with a RNG. Randomness of a RNG can be precisely, scientifically characterized and measured. Especially valuable is the information-theoretic provable RNG (True RNG - TRNG) which, at state of the art, seem to be possible only by use of physical randomness inherent to certain (simple) quantum systems. On the other hand, current industry standard dictates use of RNG's based on free running oscillators (FRO) whose randomness is derived from electronics noise present in logic circuits and which cannot be strictly proven. This approach is currently used in 3-rd and 4-th generation FPGA and ASIC hardware, unsuitable for realization of quantum TRNG. We compare weak and strong aspects of the two approaches and discuss possibility of building quantum TRNG in the recently appeared Mixed Signal FPGA technology. Finally, we discuss several examples where use of a TRNG is critical and show how it can significantly improve security of cryptographic systems.