Finding optimal quantum annealer architectures

Jincheng Zhang

This paper proposes a novel approach to deep learning model architecture design by leveraging the principles of quantum annealing. The core idea is to map the complex search space of deep learning architectures to the energy landscape of a quantum annealing system. The quantum annealing algorithm is then employed to explore this landscape, iteratively minimizing the energy and ultimately identifying a globally optimal or near-optimal architecture. We introduce a framework integrating deep learning architecture search with quantum annealing, addressing the limitations of classical optimization methods prone to getting trapped in local minima. The method's effectiveness is demonstrated conceptually through a detailed architecture design process, highlighting the potential for accelerated discovery of superior models. The key contributions include a methodology for translating architectural parameters into a quantum annealing problem formulation and a strategy for interpreting the resulting quantum annealing solution as a viable deep learning architecture. Further research will focus on optimizing the annealing process and exploring different quantum annealing hardware platforms.

Steven J. Weber, Gabriel Samach, Danna Rosenberg +4 more

Dennis Willsch

Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama

Quantum annealing (QA) is used to find the global optimum for combinatorial optimization problems. QA can be simulated on a computer using quantum Monte Carlo (QMC) simulation while spending a huge processing time. We propose a custom architecture to accelerate simulated QA. The proposed architecture is implemented using “open computing language (OpenCL)” on an Intel Aria10 FPGA. It is possible to design the most appropriate architecture for different optimization problems by changing the design parameters of the OpenCL code. We achieved over 1.94 times speed-up compared to CPU-based implementation.

Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama

Quantum Annealing (QA) is a classical probabilistic algorithm that provides a heuristic to find the globally optimal solution for a combinatorial optimization problem by using quantum tunneling processes. Quantum annealing simulation can be implemented on Field Programmable Gate Arrays (FPGAs) using Quantum Monte Carlo (QMC) simulation in the transverse Ising model. Since input data of the QMC simulation increases exponentially with the problem size, we have to use the DRAM of an FPGA board to store these data. However, storing data in DRAM causes two problems. One is the limited data access bandwidth, and the other is the limitation of DRAM capacity. We propose a data-transfer-bottleneck-less FPGA-based accelerator for quantum annealing simulation and apply it to implement number partitioning problem, which is one of the combinatorial optimization problems. The critical idea of our architecture is not storing but computing the large data in FPGA kernels and eliminating the burden on data transfer. We implement the proposed architecture on Stratix 10 FPGA and achieve up to 39.6 times speed-up compared to CPU-based quantum annealing simulation. We also achieve up to 2.8 times speed-up and implement 262,144 spins, which is 64 times increase compared to the most recent FPGA implementation.

Yu Chen, Chris Quintana, Dvir Kafri +9 more