Reversible Logic has been an emerging topic of research for the last decade and has witnessed a substantial amount of work related to synthesis algorithms, optimization techniques and Boolean circuits. Considerable amount of reversible binary arithmetic designs have been proposed. 2's complement addition forms a fundamental arithmetic operation. This present communication proposes a novel reversible Two's Complement Gate (TCG) which can directly constitute a reversible adder/subtractor design. We provide the Toffoli representation of the gate for its plausible quantum realization. We also provide the quantum metric analysis for evaluation of our proposed gate. The proposed gate has also been implemented using Quantum-Dot Cellular Automata. Comparison with an existing proposal in literature has been done and the TCG gate has been observed to excel over the counterpart.
Reversible Logic has been an emerging topic of research for the last decade and has witnessed a substantial amount of work related to synthesis algorithms, optimization techniques and Boolean circuits. Considerable amount of reversible binary arithmetic designs have been proposed. 2's complement addition forms a fundamental arithmetic operation. This present communication proposes a novel reversible Two's Complement Gate (TCG) which can directly constitute a reversible adder/subtractor design. We provide the Toffoli representation of the gate for its plausible quantum realization. We also provide the quantum metric analysis for evaluation of our proposed gate. The proposed gate has also been implemented using Quantum-Dot Cellular Automata. Comparison with an existing proposal in literature has been done and the TCG gate has been observed to excel over the counterpart.
The emerging field of Quantum Computing is still in its infancy stage. Much research has been done to develop application specific quantum gates for combinational and arithmetic logic. Still, there are shortcomings in this inventory of designs. In this paper, a Toffoli representation is provided for quantum implementation in both simulation as well as execution on an IBM quantum computer. Quantum metrics are provided for analysis of the proposed quantum gate design. The work presented here is an attempt to fill a single deficiency in this repertoire with the proposal of a Four Bit, One's Complement, Quantum Gate (OCQG-4B). This quantum gate design is both novel and reversible.
The futuristic computing is desired to be more power full with low-power consumption.That is why quantum computing has been a key area of research for quite some time and is getting more and more attention.Quantum logic being reversible, a significant amount of contributions has been reported on reversible logic in recent times.Reversible circuits are essential parts of quantum computers, and hence their designs are of great importance.In this paper, designs of reversible circuits are proposed using a recently proposed reversible gate for arithmetic and logic operations to implement various micro-operations (simple add and subtract, add with carry, subtract with borrow, transfer, incrementing, decrementing etc., and logic operations like XOR, XNOR, complementing etc.) in a reversible computer like quantum computer.The two new reversible designs proposed here for half adder and full adders are also used in the presented reversible circuits to implement various microoperations.The quantum costs of these designs are comparable.Many of the implemented micro-operations are not seen in previous literatures.The performances of the proposed circuits are compared with existing designs wherever available.
Throughout the last decade, reversible logic has been an emerging research topic. Over the years, a considerable number of application specific new reversible gates with varied characteristics have been proposed. Barring few, most of the gates lack fundamental quantum mapping in contemporary literature. This paper takes into account the four variable reversible gates those have been proposed and provides the Toffoli mapping using positive control lines. The authors optimize the designs using negative control lines wherever possible. The quantum cost, quantum gate count and two-qubit gate count required to implement those reversible gates have been provided which will set a benchmark for optimized gate choice for complex Boolean realizations. The authors also provide Hamming Distance based Complexity analysis.
The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed design 1 show appreciable improvements over gate count, quantum cost, and delay by at least 9 %, 17 %, and 26 % respectively, whereas, the proposed design 2 show that the results significantly improve the parameters (gate count, quantum cost, and delay) by at least 45 %, 33 %, and 50 % respectively compared to existing counterparts found in the literature.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
In this research work, the transistor level implementation and QCA implementation of TR reversible gate are performed and a comparison between both techniques on the ground of Area is executed. In the later section, a new-fangled design of the reversible adder and subtractor RSG gate is presented. This novel architecture can perform addition and subtraction operation simultaneously, which was never performed before using any of the existing reversible circuits. The proposed novel reversible gate, which uses 2X2 quantum gates and has a quantum cost of five, can be operated as Reversible Half Adder as well as Half Subtractor concurrently. The reversible gate proposed in this research will find numerous applicability in several DSP applications where half adder and half subtractor operates simultaneously.