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IEEE Transactions on Circuits & Systems II Express Briefs

Memory-Reduced Non-Binary LDPC Decoding With Accumulative Bubble Check

Injun Choi, Ji-Hoon Kim

Published Oct 10, 2017• 4 citations
Publisher

Abstract

Non-binary (NB) low-density parity check (LDPC) codes offer stronger error correcting capability than binary LDPC codes. However, the improvement is accompanied by a considerable increase in the decoding complexity and a huge memory requirement, especially in the check node (CN). To overcome these limitations, we propose a memory-reduced NB-LDPC decoding method with an accumulative bubble check (a-bubble check) algorithm. The proposed a-bubble check reduces the memory requirements of the CNs by using the differences between the log-likelihood ratio entries. In addition, we propose a non-uniform memory structure to further decrease the memory capacity of the CN processor. For the GF(64)(160, 80) NB-LDPC code, the proposed memory-reduced NB-LDPC decoding architecture achieves a memory requirement reduction of 32.4% for the CNs and 16.2% for the entire decoder without degrading the error correction capability.

DOI
10.1109/tcsii.2017.2761790

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IEEE Communications Letters•Nov 1, 2016•16 citations
Non-binary (NB) low-density parity check (LDPC) codes offer stronger error correcting capability than binary LDPC codes. However, the improvement is accompanied by a considerable increase in the decoding complexity and a huge memory requirement, especially in the check node (CN). To overcome these limitations, we propose a memory-reduced NB-LDPC decoding method with an accumulative bubble check (a-bubble check) algorithm. The proposed a-bubble check reduces the memory requirements of the CNs by using the differences between the log-likelihood ratio entries. In addition, we propose a non-uniform memory structure to further decrease the memory capacity of the CN processor. For the GF(64)(160, 80) NB-LDPC code, the proposed memory-reduced NB-LDPC decoding architecture achieves a memory requirement reduction of 32.4% for the CNs and 16.2% for the entire decoder without degrading the error correction capability.
Non-binary low-density parity-check (NB-LDPC) codes outperform their binary counterparts in some cases, but their high decoding complexity is a significant hurdle to their applications. In this paper, we propose a decoding algorithm with reduced computational complexities and smaller memory requirements for NB-LDPC codes over large fields. First, a simplified algorithm is proposed to reduce the computational complexity of variable node processing. To reduce memory requirements, existing NB-LDPC decoders often truncate the message vectors to a limited number nmof values. However, the memory requirements of these decoders remain high when the field size is large, since nmneeds to be large enough to alleviate error performance degradation. In this paper, an improved trellised based check node processing algorithm is proposed to significantly reduce the memory requirement. The number of elements in a variable-to-check message is reduced to nv(nvm). The sorted log likelihood ratio (LLR) vector of a check-to-variable message is approximated using a piece-wise linear function. Thus, only few LLRs are stored and other LLRs are computed on-the-fly when needed. For each a priori message, most LLRs are approximated with a linear function. Our numerical results demonstrate that the proposed decoding algorithm outperforms existing algorithms. Two LLR generation units (LGUs) are proposed to compute LLR vectors for check-to-variable messages, and the two LGUs require only a fraction of the area needed to store nmLLRs.
When the code length is moderate, non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity. The check node processing is a major bottleneck of NB-LDPC decoding. Its computation complexity can be reduced by an iterative forward-backward scheme. Nevertheless, large memory is required in this scheme to store intermediate results. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding. The proposed scheme first sorts out a limited number of the most reliable input messages. Then the forward and backward processes are carried out using only these messages. In addition, an innovative approach is developed to derive the output messages from only a small number of intermediate results without noticeable performance loss. Accordingly, both the memory requirement and computation complexity are greatly reduced. For an example (837, 726) NB-LDPC code over GF(25), our proposed check node processing architecture can achieve at least 34% area reduction and about the same throughput compared to previous efforts based on the original forward-backward scheme.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate. Check node processing is one bottleneck in NB-LDPC decoding. Various techniques have been proposed to simplify the check node processing. Particularly, the computation complexity can be reduced by employing an iterative forward-backward scheme. However, this scheme requires large memory to store intermediate results. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding. The proposed scheme first chooses a limited number of variable-to-check messages, then the check-to-variable messages to all connected variable nodes are generated independently. Employing the proposed architecture, the area requirement of the check node processing for an (837, 726) NB-LDPC code over GF (25) can be reduced to 22.5% of that of the previous work with the same processing speed and error-correcting performance.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding algorithm. The proposed scheme first sorts out a limited number of the most reliable variable-to-check (v-to-c) messages, then the check-to-variable (c-to-v) messages to all connected variable nodes are derived independently from the sorted messages without noticeable performance loss. Compared to the previous iterative forward-backward check node processing, the proposed scheme not only significantly reduced the computation complexity, but eliminated the memory required for storing the intermediate messages generated from the forward and backward processes. Inspired by this novel c-to-v message computation method, we propose to store the most reliable v-to-c messages as “compressed” c-to-v messages. The c-to-v messages will be recovered from the compressed format when needed. Accordingly, the memory requirement of the overall decoder can be substantially reduced. Compared to the previous Min-max decoder architecture, the proposed design for a (837, 726) code overGF(25) can achieve the same throughput with only 46% of the area.
Non-binary low-density parity-check (NB-LDPC) codes can achieve higher coding gain than binary LDPC codes when the code length is moderate at the cost of higher complexity. One major step of NB-LDPC decoding is check node processing. Previously, iterative forward-backward approaches are employed to implement this step. However, the storage of the intermediate results of the forward and backward computations requires large memory. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the extended Min-sum NB-LDPC decoding. The proposed scheme only stores a limited number of sorted variable-to-check messages. Then the check-to-variable messages for different variable node are generated independently. For a (837, 726) NB-LDPC code over GF(25), the proposed architecture only requires 64% of the area of the previous design with the same throughput and error-correcting performance.
This letter proposes two methods to improve the iterative hard-reliability based majority-logic decoding algorithm for non-binary low-density parity-check (NB-LDPC) codes. The first method improves the error-correcting performance by modifying the initialization process, which is based on the fact that Gray coded modulation is used in general. In addition, a storage reduction method is proposed to make the proposed decoding hardware-friendly, which reduces the memory size considerably while sustaining the error-correcting performance achieved by the modified initialization. For an NB-LDPC code over Galois field of 32 elements, the memory size is reduced by about 75% compared with that of the conventional decoding algorithm.