SFQ TDCを用いた Josephson / CMOS ハイブリッドメモリのアクセスタイム測定

Pascal Febvre

Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa

We have been developing Josephson-CMOS hybrid memory to realize large-scale single-flux-quantum (SFQ) digital systems. In this article, we present the first demonstration of a Josephson-cryo complementary-metal-oxide-semicoductor (CMOS) memory hybrid system composed of an SFQ microprocessor and cryo-CMOS memory. We designed a single-instruction SFQ microprocessor whose data memory is implemented using Josephson-CMOS hybrid memory with a 16 × 4-b accessible address space. The Josephson and CMOS circuits were fabricated using the AIST Nb standard process and the Rohm 180-nm process, respectively. Low-frequency tests confirmed the correct operation of the single instruction SUBNEG (subtract and branch if negative), which verifies the read and write operations of data between the SFQ microprocessor and the hybrid memory. We also demonstrate the operation of an integer sorting program, which is composed of 16 SUBNEG instructions.

悠史 岡本, 煕中 朴, 賢珠 陳 +3 more

悠史 岡本, 熙中 朴, 賢珠 陳 +3 more

Seda Demirhan, Ali Bozbey

Single flux quantum (SFQ) digital circuits have shown the potential for high speed/low power computation applications. Unfortunately, because of the low integration density and low driving capability of SFQ circuits, realizing large-scale memories by using only SFQ circuits is still a challenge. Josephson-CMOS hybrid memory, hybridizing high-speed, low power SFQ circuits, and high-density CMOS memories is already proposed as a solution to the large-scale memory problem in RSFQ digital systems. In this article, an SFQ-based memory controller which works up to 10 GHz clock frequencies is designed for Josephson-CMOS hybrid memory systems. The memory controller acts as a SFQ/CMOS interface between the SFQ circuit and SRAM module and generates the required waveforms for SRAM read and write operations. The circuit which has 4-b data and 2-b address lines is fabricated with AIST 2.5 kA/cm2STP2 process and operations of the circuits are verified. To demonstrate the scalability of the circuit, memory controller was scaled to 8-b data and 13-b address to control of the 64kb SRAM. Operations of the scaled memory controller are verified with analog simulations. Scaled circuit consumes 0.76 mW power in an area of 1.64 mm × 1.60 mm.

宣彰 河合, 悠史 岡本, 賢珠 陳 +2 more