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A Novel Decoding Approach for Non-Binary LDPC Codes in Finite Fields

Apurva Anand, P. Senthilkumar

Published Aug 14, 2012• 0 citations
OpenAlex

Abstract

In this paper we propose an integrated version of EMS (Extended Min-Sum) and layeredturbo decoding in Low density Parity Check Codes. Algorithmic complexity and memory problems are the major problem faced in NB-LDPC. This can be reduced by EMS algorithm under logarithm domain in the order of ( n m log 2 n m ). Speed is increased by using layered turbo scheduled decoding algorithm. Efficient implementation of non-binary LDPC decoders is a progressing field which is updated currently. This paper is based on (1) the hardware implementation costs for NB-LDPC decoders with Galois field (8,16,128,256) on FPGA and (2) To set the noise threshold very close to the theoretical maximum (Shannon Limit).

Related papers

Low Complexity Decoding Algorithms and Architectures for Non Binary LDPC Codes

M. Sravan Kumar, Abhiroop Satheesh

In this paper we propose an integrated version of EMS (Extended Min-Sum) and layered turbo decoding in Low density Parity Check Codes. Algorithmic complexity and memory problems are the major problem faced in NB-LDPC. This can be reduced by EMS algorithm under logarithm domain in the order of (􀝊m log2 􀝊m).Speed is increased by using layered turbo scheduled decoding algorithm. Efficient implementation of non-binary LDPC decoders is a progressing field which is updated currently. This paper is based on (1) the hardware implementation costs for NB-LDPC decoders with Galois field(8,16,128,256) on FPGA and (2) To set the noise threshold very close to the theoretical maximum (Shannon Limit). Keywords: NB-LDPC; EMS; layered turbo scheduled decoding algorithm; BP

•Nov 10, 2015•0 citations

LOW COMPLEXITY DESIGN OF NON-BINARY LDPC DECODER USING EXTENDED MIN-SUM ALGORITHM

C.S.Elamaran

Low Density Parity Check (LDPC) codes, is a linear block code having the decoding performance closer to Shannon's limit.Nonbinary LDPC is the class of binary LDPC, which works on the higher order Galois field.The decoding performance of non-binary (NB) LDPC is better than binary LDPC for moderate code lengths.The increased computation with the increased order of field is the major challenge in hardware realization of NB-LDPC.The extension of conventional sum-product algorithm, known as extended Min-Sum (EMS) algorithm, with reduced computational complexity is used in this paper.However, a tradeoff exists between computational complexity and decoding performance. This paper aims at reducing the computational complexity by focusing on the Parity Check Matrix (PCM) modifications. The bottleneck of the design is large memory requirement and more computation intensive. The modification in the EMS algorithm can be incorporated to design low complexity hardware architecture of NB-LDPC decoder.

International Journal of Research in Engineering and Technology•Apr 25, 2015•1 citation

Decoder Design for Non-Binary LDPC Codes

Fei Liu, Haitao Li

Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. In this paper, we give the different initial step for different modulation and present a hardware implementation of the extended min-sum (EMS) decoding algorithm for non-binary LDPC codes. Moreover, an FPGA simulation over GF(16) is given to demonstrate the efficiency of the presented techniques.

International Conference on Wireless Communications, Networking and Mobile Computing•Sep 1, 2011•1 citation

Low-complexity decoding for non-binary LDPC codes in high order fields

Adrian Voicila, David Declercq, François S. Verdier +2 more

In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number nmof values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to ¿(nmlog2nm). This complexity starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation is quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual simulations.

IEEE Transactions on Communications•May 1, 2010•223 citations

Decoding Algorithms for Nonbinary LDPC Codes Over GF$(q)$

David Declercq, M.P.C. Fossorier

In this letter, we address the problem of decoding nonbinary low-density parity-check (LDPC) codes over finite fields GF(q), with reasonable complexity and good performance. In the first part of the letter, we recall the original belief propagation (BP) decoding algorithm and its Fourier domain implementation. We show that the use of tensor notations for the messages is very convenient for the algorithm description and understanding. In the second part of the letter, we introduce a simplified decoder which is inspired by the min-sum decoder for binary LDPC codes. We called this decoder extended min-sum (EMS). We show that it is possible to greatly reduce the computational complexity of the check-node processing by computing approximate reliability measures with a limited number of values in a message. By choosing appropriate correction factors or offsets, we show that the EMS decoder performance is quite good, and in some cases better than the regular BP decoder. The optimal values of the factor and offset correction are obtained asymptotically with simulated density evolution. Our simulations on ultra-sparse codes over very-high-order fields show that nonbinary LDPC codes are promising for applications which require low frame-error rates for small or moderate codeword lengths. The EMS decoder is a good candidate for practical hardware implementations of such codes

IEEE Transactions on Communications•Apr 1, 2007•724 citations

High throughput and low complexity implementation of NB-LDPC decoder based on EMS algorithm

Sun Shu long, Lin Min

Non-Binary Low-Density-Parity-Check codes (NB-LDPC) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasi-cyclic NB-LDPC decoder over GF (16) based on Extended Min-Sum (EMS) Algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binary LDPC code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.

IEICE Electronics Express•Jan 1, 2016•0 citations
In this paper we propose an integrated version of EMS (Extended Min-Sum) and layeredturbo decoding in Low density Parity Check Codes. Algorithmic complexity and memory problems are the major problem faced in NB-LDPC. This can be reduced by EMS algorithm under logarithm domain in the order of ( n m log 2 n m ). Speed is increased by using layered turbo scheduled decoding algorithm. Efficient implementation of non-binary LDPC decoders is a progressing field which is updated currently. This paper is based on (1) the hardware implementation costs for NB-LDPC decoders with Galois field (8,16,128,256) on FPGA and (2) To set the noise threshold very close to the theoretical maximum (Shannon Limit).
In this paper we propose an integrated version of EMS (Extended Min-Sum) and layered turbo decoding in Low density Parity Check Codes. Algorithmic complexity and memory problems are the major problem faced in NB-LDPC. This can be reduced by EMS algorithm under logarithm domain in the order of (􀝊m log2 􀝊m).Speed is increased by using layered turbo scheduled decoding algorithm. Efficient implementation of non-binary LDPC decoders is a progressing field which is updated currently. This paper is based on (1) the hardware implementation costs for NB-LDPC decoders with Galois field(8,16,128,256) on FPGA and (2) To set the noise threshold very close to the theoretical maximum (Shannon Limit). Keywords: NB-LDPC; EMS; layered turbo scheduled decoding algorithm; BP
Low Density Parity Check (LDPC) codes, is a linear block code having the decoding performance closer to Shannon's limit.Nonbinary LDPC is the class of binary LDPC, which works on the higher order Galois field.The decoding performance of non-binary (NB) LDPC is better than binary LDPC for moderate code lengths.The increased computation with the increased order of field is the major challenge in hardware realization of NB-LDPC.The extension of conventional sum-product algorithm, known as extended Min-Sum (EMS) algorithm, with reduced computational complexity is used in this paper.However, a tradeoff exists between computational complexity and decoding performance. This paper aims at reducing the computational complexity by focusing on the Parity Check Matrix (PCM) modifications. The bottleneck of the design is large memory requirement and more computation intensive. The modification in the EMS algorithm can be incorporated to design low complexity hardware architecture of NB-LDPC decoder.
In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration. The key feature of our decoder is to truncate the vector messages of the decoder to a limited number nmof values in order to reduce the memory requirements. Using the truncated messages, we propose an efficient implementation of the EMS decoder which reduces the order of complexity to ¿(nmlog2nm). This complexity starts to be reasonable enough to compete with binary decoders. The performance of the low complexity algorithm with proper compensation is quite good with respect to the important complexity reduction, which is shown both with a simulated density evolution approach and actual simulations.
Decoding Algorithms for Nonbinary LDPC Codes Over GF(q)(q)(q)
In this letter, we address the problem of decoding nonbinary low-density parity-check (LDPC) codes over finite fields GF(q), with reasonable complexity and good performance. In the first part of the letter, we recall the original belief propagation (BP) decoding algorithm and its Fourier domain implementation. We show that the use of tensor notations for the messages is very convenient for the algorithm description and understanding. In the second part of the letter, we introduce a simplified decoder which is inspired by the min-sum decoder for binary LDPC codes. We called this decoder extended min-sum (EMS). We show that it is possible to greatly reduce the computational complexity of the check-node processing by computing approximate reliability measures with a limited number of values in a message. By choosing appropriate correction factors or offsets, we show that the EMS decoder performance is quite good, and in some cases better than the regular BP decoder. The optimal values of the factor and offset correction are obtained asymptotically with simulated density evolution. Our simulations on ultra-sparse codes over very-high-order fields show that nonbinary LDPC codes are promising for applications which require low frame-error rates for small or moderate codeword lengths. The EMS decoder is a good candidate for practical hardware implementations of such codes
Non-Binary Low-Density-Parity-Check codes (NB-LDPC) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasi-cyclic NB-LDPC decoder over GF (16) based on Extended Min-Sum (EMS) Algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binary LDPC code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.