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Journal of advances in computer research

Search Based Weighted Multi-Bit Flipping Algorithm for High-Performance Low-Complexity Decoding of LDPC Codes

Ehsan Olyaei Torshizi, Mohammad Amir Nazari Siahsar, Ali Akbar Khazaei, Hossein Sharifi

Published Feb 1, 2018• 0 citations
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n Improved Multi-Bit Threshold Flipping LDPC Decoding Algorithm

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In this paper, a new two-stage hybrid algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed that incorporates two iterative decoding. For the first stage of decoding, we offer a new decoding algorithm called Improved Variable Multi Weighted Bit-Flipping (IVMWBF) algorithm. Since the IVMWBF algorithm is based on the idea of flipping variable multi bits in each iteration, both improvement in performance and reduction in iteration number and computational complexity are observed in this algorithm. The proposed hybrid algorithm which is a combination of the IVMWBF and BP algorithms, while having a performance exactly similar to that of the BP algorithm, has less complexity compared to that algorithm.
Aiming at seeking a low-complexity decoder with fast decoding convergence speed for short or medium low-density parity-check (LDPC) codes, an improved parallel weighted bit-flipping (IPWBF) algorithm, which is applied flexibly for two classes of codes is presented here. For LDPC codes with low column weight in their parity check matrix, both bootstrapping and loop detection procedures, described in the existing literature, are included in IPWBF. Furthermore, a novel delay-handling procedure is introduced to prevent the codeword bits of high reliability from being flipped too hastily. For large column weight finite geometry LDPC codes, only the delay-handling procedure is included in IPWBF to show its effectiveness. Extensive simulation results demonstrate that the proposed algorithm achieves a good tradeoff between performance and complexity.
VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.