Many disciplines, such as antenna beam-forming and \nadaptive optics, require the ability to perform high \nspeed matrix operations, which often can be reduced to a \nseries of matrix-vector products. Analog optical matrixvector \nprocessors (OMVP's) take advantage of the high \nspeed and parallelism of optics to rapidly compute \nmatrix-vector products. However, OMVP's suffer from a \nlow accuracy which currently hinders their widespread \napplication. Over the past decade, various techniques \nhave been introduced to achieve high accuracy computation \nwith OMVP's. This dissertation studies the application \nof error-correcting codes (ECC's) and the union of ECC's \nwith digital partitioning to achieve high accuracy computation. \nThe ability of ECC's to improve the performance \nof OMVP's is studied through the use of computer simulations. \nThe effect ECC's have on system throughput is \nalso studied. Digital partitioning is a new technique \nfor achieving high accuracy computations on analog \nOMVP's. One potential drawback of digital partitioning \nis its sensitivity to errors. Error-correcting codes can \nenhance the performance of the digital partitioning algorithm \nby reducing this sensitivity to errors. Computer \nsimulation results are presented showing the benefits of \nusing ECC's with digital partitioning. In addition, an \nanalysis of the time requirements for encoding and decoding \nthe ECC's and the effect on system throughput is \npresented.
Many disciplines, such as antenna beam-forming and \nadaptive optics, require the ability to perform high \nspeed matrix operations, which often can be reduced to a \nseries of matrix-vector products. Analog optical matrixvector \nprocessors (OMVP's) take advantage of the high \nspeed and parallelism of optics to rapidly compute \nmatrix-vector products. However, OMVP's suffer from a \nlow accuracy which currently hinders their widespread \napplication. Over the past decade, various techniques \nhave been introduced to achieve high accuracy computation \nwith OMVP's. This dissertation studies the application \nof error-correcting codes (ECC's) and the union of ECC's \nwith digital partitioning to achieve high accuracy computation. \nThe ability of ECC's to improve the performance \nof OMVP's is studied through the use of computer simulations. \nThe effect ECC's have on system throughput is \nalso studied. Digital partitioning is a new technique \nfor achieving high accuracy computations on analog \nOMVP's. One potential drawback of digital partitioning \nis its sensitivity to errors. Error-correcting codes can \nenhance the performance of the digital partitioning algorithm \nby reducing this sensitivity to errors. Computer \nsimulation results are presented showing the benefits of \nusing ECC's with digital partitioning. In addition, an \nanalysis of the time requirements for encoding and decoding \nthe ECC's and the effect on system throughput is \npresented.
Optical algebraic processors can perform complex calculations in parallel and at high speeds. However, they commonly suffer from a low analog accuracy which hinders their widespread application. Error detection and correction codes provide one technique for improving the accuracy of optical algebraic processors. The use of these codes would allow some of the errors that may occur during a computation to be detected and possibly corrected. This paper describes the results of various computer simulations of optical matrix-vector multipliers employing error-correction codes. It discusses the application of convolutional codes to optical matrix-vector multipliers along with several block codes. Both binary and nonbinary codes are not employing error-correction codes. Also, the type of noise, whether signal-independent or signal-dependent, has a significant effect on the performance of a matrix-vector multiplier employing an error code. The encoding and decoding operations required for the error codes can be performed optically.
Optical processors can perform complex calculations in parallel at high speeds. They commonly suffer, however, from low accuracy, which currently hinders their widespread use. Various models for the noise in optical processors have been developed.1 In addition, various techniques have been developed to improve their accuracy. One technique involves the use of error-detection and correction codes to improve the accuracy of optical linear algebra processors.2 This allows some of the errors that occur during computation to be detected and possibly corrected. These codes, developed earlier for data transmission and fault tolerance in electronic processors, can thus be used to improve accuracy. Many of the required encoding and decoding operations can be performed optically. Computer simulations of optical matrix-vector multipliers employing various error codes will be presented. They indicate that a significant improvement in accuracy can be obtained when they are compared with processors not employing error codes.
Optical algebraic processors can perform complex calculations in parallel and at high speeds. However, they commonly suffer from a low analog accuracy which hinders their widespread application. Error detection and correction codes provide one technique for improving the accuracy of optical algebraic processors. The use of these codes would allow some of the errors that may occur during a computation to be detected and possibly corrected. This paper describes the results of various computer simulations of optical matrix-vector multipliers employing error-correction codes. It discusses the application of convolutional codes to optical matrix-vector multipliers along with several block codes. Both binary and nonbinary codes are considered. The results indicate that a significant improvement in performance can be obtained when compared with processors not employing error-correction codes. Also, the type of noise, whether signal-independent or signal-dependent noise, has a significant effect on the performance of a matrix-vector multiplier employing an error code. The encoding and decoding operations required for the error codes can be performed optically.
Optical matrix-vector multipliers are known to suffer from low computational accuracy which is the major drawback preventing them from becoming a practical force in real world applications. Error-correction coding is one technique proposed to overcome this problem of low level accuracy. In this thesis, the effects of the application of multiple error-correction codes to optical matrix-vector multipliers are studied. For this purpose, many different cases were simulated on a computer. Noting that an optical matrix-vector multiplier performs the product y = Ax, basically four cases were considered; signal independent and signal dependent noise in the matrix A, and signal independent and signal dependent noise in the vector x. Two different error-correcting codes were simulated; one being a binary, multiple error-correcting BCH code and other being a non-binary, multiple error-correcting Reed-Solomon code, which is basically an extension of the binary BCH code. The advantages and disadvantages of switching from binary BCH codes to non-binary Reed-Solomon codes were investigated. Based on the results obtained from the simulations, the conditions under which the use of error-correction coding is feasible in optical matrix-vector multipliers are discussed.
Photonic processors have emerged as an attractive platform for fast and energy-efficient matrix-vector multiplication. However, they are susceptible to error due to their analog nature. Here, we present an error-correction technique that implements a correction offset to the optical en-/decoders of photonic processors. Our proposed method is general-purpose, does not require introducing any additional components to the photonic network, and can address errors stemming from unbalanced losses, 50/50 beamsplitter deviations, digital-to-analog conversion inaccuracies, and any unknown sources. In particular, we show that our method is highly effective in mitigating unbalanced-loss errors, a problem that has not previously been addressed by any error-correction technique. Using this approach, we achieve over 90% error reduction in large triangular meshes, overcoming a key obstacle to highly accurate photonic processors for information processing.
Error correctiong codes (ECC) are widly used in applications to correct errors in data transmission over unreliable or noisy communication channels. Recently, two kinds of promising codes attracted lots of research interest because they provide excellent error correction performance. One is non-binary LDPC codes, and the other is polar codes. This dissertation focuses on efficient decoding algorithms and decoder design for thesetwo types of codes.Non-binary low-density parity-check (LDPC) codes have some advantages over their binary counterparts, but unfortunately their decoding complexity is a significant challenge. The iterative hard- and soft-reliability based majority-logic decoding algorithms are attractive for non-binary LDPC codes, since they involve only finite field additions and multiplications as well as integer operations and hence have significantly lower complexity than other algorithms. We propose two improvements to the majority-logic decoding algorithms. Instead of the accumulation of reliability information in the ex-isting majority-logic decoding algorithms, our first improvement is a new reliability information update. The new update not only results in better error performance and fewer iterations on average, but also further reduces computational complexity. Since existing majority-logic decoding algorithms tend to have a high error floor for codes whose parity check matrices have low column weights, our second improvement is a re-selection scheme, which leads to much lower error floors, at the expense of more finite field operations and integer operations, by identifying periodic points, re-selectingintermediate hard decisions, and changing reliability information.Polar codes are of great interests because they provably achieve the symmetric capacity of discrete memoryless channels with arbitrary input alphabet sizes an explicit construction. Most existing decoding algorithms of polar codes are based on bit-wise hard or soft decisions. We propose symbol-decision successive cancellation (SC) and successive cancellation list (SCL) decoders for polar codes, which use symbol-wise hard or soft decisions for higher throughput or better error performance. Then wepropose to use a recursive channel combination to calculate symbol-wise channel transition probabilities, which lead to symbol decisions. Our proposed recursive channel combination has lower complexity than simply combining bit-wise channel transition probabilities. The similarity between our proposed method and Arıkan's channel transformations also helps to share hardware resources between calculating bit- and symbol-wise channel transition probabilities. To reduce the complexity of the list pruning, atwo-stage list pruning network is proposed to provide a trade-off between the error performance and the complexity of the symbol-decision SCL decoder. Since memory is a significant part of SCL decoders, we also propose a pre-computation memory-saving technique to reduce memory requirement of an SCL decoder.To reduce the complexity of the recursive channel combination further, we propose an approximate ML (AML) decoding unit for SCL decoders. In particular, we investigate the distribution of frozen bits of polar codes designed for both the binary erasure and additive white Gaussian noise channels, and take advantage of the distribution to reduce the complexity of the AML decoding unit, improving the throughput-area efficiency of SCL decoders.Furthermore, to adapt to variable throughput or latency requirements which exist widely in current communication applications, a multi-mode SCL decoder with variable list sizes and parallelism is proposed. If high throughput or small latency is required, the decoder decodes multiple received words in parallel with a small list size. However, if error performance is of higher priority, the multi-mode decoder switches to a serialmode with a bigger list size. Therefore, the multi-mode SCL decoder provides a flexible tradeoff between latency, throughput and error performance at the expense of small overhead.