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IEEE Transactions on Applied Superconductivity

Energy-Efficient and Compact ERSFQ Decoder for Cryogenic RAM

I. V. Vernik, Alex F. Kirichenko, Oleg A. Mukhanov, Thomas Ohki

Published Dec 30, 2016• 22 citations
Publisher

Abstract

We report on the development of energy-efficient decoders for cryogenic random access memory and register file. To reduce the pitch, area, and energy, our decoder employs a scalable binary tree architecture. We implemented these decoders using ERSFQ logic controlled by magnetically coupled address lines. These lines are driven by energy-efficient drivers based on the current-stirring technique. A 4-to-16 version of the decoder was laid out and fabricated in HYPRES 6-layer 10 kA/cm2and MIT LL 8-layer 10 kA/cm2processes with 15 and 28 μm decoder row pitch, respectively. The decoders were designed to have ~30 ps latency and dissipate ~40 aJ per clock. We experimentally confirmed the functionality of the circuits with ±8% dc bias margins and verified its operation up to 13 GHz clock.

DOI
10.1109/tasc.2016.2646926

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IEEE Transactions on Applied Superconductivity•Dec 30, 2016•40 citations
We report on the development of energy-efficient decoders for cryogenic random access memory and register file. To reduce the pitch, area, and energy, our decoder employs a scalable binary tree architecture. We implemented these decoders using ERSFQ logic controlled by magnetically coupled address lines. These lines are driven by energy-efficient drivers based on the current-stirring technique. A 4-to-16 version of the decoder was laid out and fabricated in HYPRES 6-layer 10 kA/cm2and MIT LL 8-layer 10 kA/cm2processes with 15 and 28 μm decoder row pitch, respectively. The decoders were designed to have ~30 ps latency and dissipate ~40 aJ per clock. We experimentally confirmed the functionality of the circuits with ±8% dc bias margins and verified its operation up to 13 GHz clock.
We designed, fabricated, and demonstrated an energy-efficient ERSFQ 4-bit decoder. The first version of the decoder is designed and fabricated using HYPRES legacy 1.0-μm four-layer 4.5-kA/cm2process. It occupies an area of 700 μm × 1800 μm, which is to be reduced to 160 μm × 400 μm once fabricated using HYPRES's RIPPLE-2 0.25-μm six-layer process. The decoder features ±13% dc bias current operating margins and below 70-aJ energy consumption per one address select operation. We report test results of the decoder and discuss its future implementation in cryogenic random access memory devices, including magnetic memory devices.
We present the design and test results of components for a superconductor Cryogenic Random Access Memory (CRAM). The 16-Kb RAM design consists of four 4-Kb sub-arrays (blocks) with a 400 ps access time (latency) and a 100 ps cycle time (throughput). Each 4-Kb RAM block comprises a row-accessed 32/spl times/128 memory cell array, bipolar line drivers, row decoders, and column sense circuits. The implementation of specially designed distributed Josephson junctions in the sensing circuits reduces the overall size of the blocks and allows the use of smaller dc control currents.
We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm2process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm2process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm2planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm2process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.
We designed and tested low-power digital gates based on the energy-efficient rapid single flux quantum (ERSFQ) and on the reversible nSQUID logic. The ERSFQ circuit consists of a series of 13 toggle flip-flops (TFFs), where the bias resistors are replaced by inductors which generate no energy dissipation in the static mode, resulting in a power consumption orders of magnitude below that of traditional RSFQ circuits during operation. The ERSFQ circuits were fabricated with HYPRES' standard 4.5-kA/cm2process and tested up to 20 GHz. The RF input level was about -25 dBm 50 Ω matched, and the output level was 400 μVpp. The nSQUID ring with “NOT” gates was fabricated with HYPRES' standard 1-kA/cm2process. The “0” and “1” input logic signals were realized injecting ±5 mA of current in a superconductive coil, obtaining 6 μVpp of amplitude as output signal. The test was performed at low frequency in order to verify the functionality and the ultralow power consumption.
We have designed and tested a parallel 8-bit ERSFQ binary shifter that is one of the essential circuits in the design of the energy-efficient superconducting CPU. The binary shifter performs a bidirectional SHIFT instruction of an 8-bit argument. It consists of a bidirectional triple-port shift register controlled by two (left and right) shift pulse generators asynchronously generating a set number of shift pulses. At first clock cycle, an 8-bit word is loaded into the binary shifter and a 3-bit shift argument is loaded into the desired shift-pulse generator. Next, the generator produces the required number of shift SFQ pulses (from 0 to 7) asynchronously, with a repetition rate set by the internal generator delay of ~ 30 ps. These SFQ pulses are applied to the left (positive) or the right (negative) input of the binary shifter. Finally, after the shift operation is completed, the resulting 8-bit word goes to the parallel output. The complete 8-bit ERSFQ binary shifter, consisting of 820 Josephson junctions, was simulated and optimized using PSCAN2. It was fabricated in MIT Lincoln Lab's 10-kA/cm2SFQ5ee fabrication process with a high-kinetic inductance layer. We have successfully tested the binary shifter at both the LSB-to-MSB and MSB-to-LSB propagation regimes for all eight shift arguments. A single shift operation on a single input word demonstrated operational margins of ±16% of the dc bias current. The correct functionality of the 8-bit ERSFQ binary shifter with the large, exhaustive data pattern was observed within ±10% margins of the dc bias current. In this paper, we describe the design and present the test results for the ERSFQ 8-bit parallel binary shifter.
We present hybridization of Josephson, CMOS, and nanocryotron (nTron) devices for a large-scale cryogenic memory application. The memory system proposed here is dynamic random access memory composed of address decoders based on an energy-efficient rapid single-flux-quantum logic, nTron line drivers, a CMOS memory cell array, and Josephson current sensors. Because drivers with voltage amplification and decoders are the major causes of power dissipation in the conventional Josephson-CMOS hybrid memory, drastic reduction in power consumption is expected. We show estimates that the power consumption of a 16-Mb memory is reduced to 1.36-2.77 mW, approximately 1/12 of the conventional Josephson-CMOS hybrid memory, and the access time is 0.78 ns for a read operation, when we assume a 65-nm CMOS process and a 1.0-μm Nb/AlOx/Nb process. In the preliminary experiment, we fabricated nTrons using NbTiN thin film that are suitable for hybrid memory implementation, and measured with eight-transistor static random access memory cells fabricated using the Rohm 0.18-μm CMOS process. We successfully triggered the nTron into the normal state, and observed output voltage of ~0.1 V at 13.5 K. The experimental results support the potential of the hybrid memory using NbTiN nTrons.