In almost all the Digital Signal Processing (DSP) applications, the vital operations involve multiplications and accumulations. Consequently, there is a demand for dedicated hardware in processors to enhance the speed with which these multiplications and accumulations are performed. In the present world of irreversible circuits, the Multiply Accumulate Unit multiplies the two operands, adds the product to the previously accumulated result and stores back the new result in the Accumulator all in a single clock cycle. On the other hand, implementation of digital circuits in reversible logic is gaining popularity with the arrival of quantum computing and reversible logic. In this paper, we propose a novel Reversible Multiply Accumulate (MAC) unit. We also build a Reversible Vedic MAC unit and compare various possible implementations of the reversible MAC unit in terms of Quantum Cost, number of Garbage Outputs and Depth.In almost all the Digital Signal Processing (DSP) applications, the vital operations involve multiplications and accumulations. Consequently, there is a demand for dedicated hardware in processors to enhance the speed with which these multiplications and accumulations are performed. In the present world of irreversible circuits, the Multiply Accumulate Unit multiplies the two operands, adds the product to the previously accumulated result and stores back the new result in the Accumulator all in a single clock cycle. On the other hand, implementation of digital circuits in reversible logic is gaining popularity with the arrival of quantum computing and reversible logic. In this paper, we propose a novel Reversible Multiply Accumulate (MAC) unit. We also build a Reversible Vedic MAC unit and compare various possible implementations of the reversible MAC unit in terms of Quantum Cost, number of Garbage Outputs and Depth.

International Conference on Communication, Information & Computing TechnologyOct 1, 20126 citations

Fast quantum modular exponentiation architecture for Shor's factoring alogrithm

Archimedes Pavlidis, Dimitris Gizopoulos

We present a novel and efficient, in terms of circuit depth, design for Shor's quantum factorization algorithm. The circuit effectively utilizes a diverse set of adders based on the Quantum Fourier transform (QFT) Draper's adders to build more complex arithmetic blocks: quantum multiplier/accumulators by constants and quantum dividers by constants. These arithmetic blocks are effectively architected into a quantum modular multiplier which is the fundamental block for the modular exponentiation circuit, the most computational intensive part of Shor's algorithm. The proposed modular exponentiation circuit has a depth of about $2000n^2$ and requires $9n+2$ qubits, where $n$ is the number of bits of the classic number to be factored. The total quantum cost of the proposed design is $1600n^3$ . The circuit depth can be further decreased by more than three times if the approximate QFT implementation of each adder unit is exploited.We present a novel and efficient, in terms of circuit depth, design for Shor's quantum factorization algorithm. The circuit effectively utilizes a diverse set of adders based on the Quantum Fourier transform (QFT) Draper's adders to build more complex arithmetic blocks: quantum multiplier/accumulators by constants and quantum dividers by constants. These arithmetic blocks are effectively architected into a quantum modular multiplier which is the fundamental block for the modular exponentiation circuit, the most computational intensive part of Shor's algorithm. The proposed modular exponentiation circuit has a depth of about $2000n^2$ and requires $9n+2$ qubits, where $n$ is the number of bits of the classic number to be factored. The total quantum cost of the proposed design is $1600n^3$. The circuit depth can be further decreased by more than three times if the approximate QFT implementation of each adder unit is exploited.

Quantum Information and ComputationMay 1, 201438 citations

2000n^2

and requires

9n+2

qubits, where

n

is the number of bits of the classic number to be factored. The total quantum cost of the proposed design is

1600n^3

. The circuit depth can be further decreased by more than three times if the approximate QFT implementation of each adder unit is exploited.