A quantum multiply-accumulator

Hafiz Md. Hasan Babu

Hafiz Md. Hasan Babu

Raman M Swaraj, Kumar K Arun, Reddy K Srinivas

In almost all the Digital Signal Processing (DSP) applications, the vital operations involve multiplications and accumulations. Consequently, there is a demand for dedicated hardware in processors to enhance the speed with which these multiplications and accumulations are performed. In the present world of irreversible circuits, the Multiply Accumulate Unit multiplies the two operands, adds the product to the previously accumulated result and stores back the new result in the Accumulator all in a single clock cycle. On the other hand, implementation of digital circuits in reversible logic is gaining popularity with the arrival of quantum computing and reversible logic. In this paper, we propose a novel Reversible Multiply Accumulate (MAC) unit. We also build a Reversible Vedic MAC unit and compare various possible implementations of the reversible MAC unit in terms of Quantum Cost, number of Garbage Outputs and Depth.

Nikolai Joukov, M.S. Tivari, Vasili K. Semenov

We have designed and successfully tested at low speed a rapid single flux quantum signed serial multiplier-accumulator with target clock frequency 20 GHz. Each bit slice of the device consists of 106 Josephson junctions and 90 resistors. It consumes 22 mA of current and occupies 0.3 mm/sup 2/. The accumulator of the developed multiplier makes two (rather than three) primitive operations per cycle without any additional overheads. This makes it fast and very robust. In particular, /spl plusmn/18% bias supply margins have been measured in a four-slice multiplier. This is our first device where superconductor microstrip lines (MSLs) have been routinely used. The MSL interfaces introduce some overhead but it is compensated by the simplicity of the design procedure.

S.S. Martinet, DARREN K. BROCK, M. J. Feldman +1 more

We are in the process of designing a Finite Impulse Response (FIR) filter for use in a Digital Signal Processing (DSP) system based entirely on Rapid Single Flux Quantum (RSFQ) logic. One aspect of this project involves the development of the arithmetic unit of the filter, in this case an adder-accumulator multiplier. This article describes two cells can perform the function of accumulated addition in the adder-accumulator multiplier. We have fabricated both cells and tested them at low speed.>

Hafiz Md. Hasan Babu