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Physical Review B

Scalable architecture for quantum information processing with superconducting flux qubits based on purely longitudinal interactions

P.-M. Billangeon, J. S. Tsai, Yasunobu Nakamura

Published Jul 20, 2015• 15 citations
Publisher

Abstract

We devise a quantum register based on superconducting flux qubits that circumvents the impediments posed by the presence of fixed interactions. We describe a coupling scheme wherein two physical qubits are coupled to a third which acts as a coupler via their longitudinal degree of freedom (i.e., ${\ensuremath{\sigma}}_{z}$). This approach provides a solution to several issues such as residual interactions between physical qubits, deteriorations of the rotating wave approximation (RWA), and correlated errors, thereby expanding the opportunities for capitalizing on the large coupling strengths achievable with these systems.

DOI
10.1103/physrevb.92.020509

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We devise a quantum register based on superconducting flux qubits that circumvents the impediments posed by the presence of fixed interactions. We describe a coupling scheme wherein two physical qubits are coupled to a third which acts as a coupler via their longitudinal degree of freedom (i.e., \ensuremathσz{\ensuremath{\sigma}}_{z}\ensuremathσz​). This approach provides a solution to several issues such as residual interactions between physical qubits, deteriorations of the rotating wave approximation (RWA), and correlated errors, thereby expanding the opportunities for capitalizing on the large coupling strengths achievable with these systems.
We discuss different ways of generating entanglement in the original picture of circuit QED (XcQED) and several restrictions that arise in the context of a large-scale quantum architecture. To alleviate some of the issues posed by the presence of the nonlinearities inherent to these systems, we introduce a layout for circuit QED, wherein an artificial atom is coupled to a quantized radiation field via its longitudinal degree of freedom (ZcQED). This system is akin to ion traps used in atomic physics, but it relies on fixed coupling between the atom and the resonator. We describe a scalable architecture for processing quantum information with superconducting qubits, which is free from any type of residual interaction between the atomic and photonic degrees of freedom. Tunable interactions can be realized based on sideband transitions, and the system can be operated out of the Lamb-Dicke regime, allowing it to benefit from the possibility of achieving large coupling strengths between atoms and resonators. We also discuss a readout scheme that does not require any extra circuits and allows a qubit-specific measurement of the state of the quantum register inspired by the electron shelving technique. This scheme is quantum nondemolition (QND)-like, and allows for single-shot determination of the qubit states.
Large-scale quantum computers will consist of many interacting qubits. In this paper we expand the two flux qubit coupling scheme first devised by P. Plourde et al. [Phys. Rev. B 70, 140501 (2004)] and realized by T. Hime et al. [Science 314, 1427 (2006)] to a three-qubit, two-coupler scenario. We study L-shaped and line-shaped coupler geometries, and show how the interaction strength between qubits changes in terms of the couplers' dimensions. We explore two cases: the ``on-state'' where the interaction energy between two nearest-neighbor qubits is high, and the ``off-state'' where it is turned off. In both situations we study the undesirable crosstalk with the third qubit. Finally, we use the grape algorithm to find efficient pulse sequences for two-qubit gates subject to our calculated physical constraints on the coupling strength.
Constructing a fault-tolerant quantum computer is a daunting task. Given any design, it is possible to determine the maximum error rate of each type of component that can be tolerated while still permitting arbitrarily large-scale quantum computation. It is an underappreciated fact that including an appropriately designed mechanism enabling long-range qubit coupling or transport substantially increases the maximum tolerable error rates of all components. With this thought in mind, we take the superconducting flux qubit coupling mechanism described by Plourde et al. [Phys. Rev. B 70, 140501(R) (2004)] and extend it to allow approximately 500MHz500\phantom{\rule{0.3em}{0ex}}\mathrm{MHz}500MHz coupling of square flux qubits, $50\phantom{\rule{0.3em}{0ex}}\ensuremath{\mu}\mathrm{m}$ a side, at a distance of up to several millimeters. This mechanism is then used as the basis of two scalable architectures for flux qubits taking into account cross-talk and fault-tolerant considerations such as permitting a universal set of logical gates, parallelism, measurement and initialization, and data mobility.
Superconducting quantum processors have largely converged on transmon-based architectures, while alternative qubit modalities with intrinsic error protection have lacked a demonstrated path to scalable system integration. In particular, although tunable-coupler-mediated interactions have been validated for small fluxonium systems, it remains unclear whether such designs can be scaled to a multi-qubit lattice. Here, we establish a scalable fluxonium processor architecture based on a modular qubit-coupler unit cell engineered to suppress residual interactions and spectator errors in a many-qubit lattice. The system enables parallel single-qubit gate fidelities approaching 99.99% and two-qubit CZ gate fidelities around 99%. With an optimized gate duration of 32 ns, the best CZ gate fidelity reaches 99.9%. We further validate this architecture in a 22-qubit processor based on the same configuration, where parallel operations enable the deterministic generation of Greenberger-Horne-Zeilinger states involving up to 10 qubits. Together, these results demonstrate that the fluxonium-tunable-coupler unit cell composes without emergent interaction pathologies and establish fluxonium as a scalable superconducting qubit platform.
Superconducting qubits are a promising platform for building fault-tolerant quantum computers, with recent achievement showing the suppression of logical error with increasing code size. However, leakage into noncomputational states, a common issue in practical quantum systems including superconducting circuits, introduces correlated errors that undermine quantum error correction (QEC) scalability. Here, we propose and demonstrate a leakage reduction scheme utilizing tunable couplers, a widely adopted ingredient in large-scale superconducting quantum processors. Leveraging the strong frequency tunability of the couplers and stray interaction between the couplers and readout resonators, we eliminate state leakage on the couplers, thus suppressing space-correlated errors caused by population propagation among the couplers. Assisted by the couplers, we further reduce leakage to higher qubit levels with high efficiency (98.1%) and low error rate on the computational subspace (0.58%), suppressing time-correlated errors during QEC cycles. The performance of our scheme demonstrates its potential as an indispensable building block for scalable QEC with superconducting qubits.
Constructing a fault-tolerant quantum computer is a daunting task. Given any design, it is possible to determine the maximum error rate of each type of component that can be tolerated while still permitting arbitrarily large-scale quantum computation. It is an under-appreciated fact that including an appropriately designed mechanism enabling long-range qubit coupling or transport substantially increases the maximum tolerable error rates of all components. With this thought in mind, we take the superconducting flux qubit coupling mechanism described in Plourde et al. (Phys. Rev. B, 70, 140501(R) (2004)) and extend it to allow approximately 500~MHz coupling of square flux qubits, 50 µm a side, at a distance of up to several mm. This mechanism is then used as the basis of two scalable architectures for flux qubits taking into account crosstalk and fault-tolerant considerations such as permitting a universal set of logical gates, parallelism, measurement and initialization, and data mobility.PACS No.: 03.67.Lx