Constructing a fault-tolerant quantum computer is a daunting task. Given any design, it is possible to determine the maximum error rate of each type of component that can be tolerated while still permitting arbitrarily large-scale quantum computation. It is an under-appreciated fact that including an appropriately designed mechanism enabling long-range qubit coupling or transport substantially increases the maximum tolerable error rates of all components. With this thought in mind, we take the superconducting flux qubit coupling mechanism described in Plourde et al. (Phys. Rev. B, 70, 140501(R) (2004)) and extend it to allow approximately 500~MHz coupling of square flux qubits, 50 µm a side, at a distance of up to several mm. This mechanism is then used as the basis of two scalable architectures for flux qubits taking into account crosstalk and fault-tolerant considerations such as permitting a universal set of logical gates, parallelism, measurement and initialization, and data mobility.PACS No.: 03.67.Lx
Constructing a fault-tolerant quantum computer is a daunting task. Given any design, it is possible to determine the maximum error rate of each type of component that can be tolerated while still permitting arbitrarily large-scale quantum computation. It is an under-appreciated fact that including an appropriately designed mechanism enabling long-range qubit coupling or transport substantially increases the maximum tolerable error rates of all components. With this thought in mind, we take the superconducting flux qubit coupling mechanism described in Plourde et al. (Phys. Rev. B, 70, 140501(R) (2004)) and extend it to allow approximately 500~MHz coupling of square flux qubits, 50 µm a side, at a distance of up to several mm. This mechanism is then used as the basis of two scalable architectures for flux qubits taking into account crosstalk and fault-tolerant considerations such as permitting a universal set of logical gates, parallelism, measurement and initialization, and data mobility.PACS No.: 03.67.Lx
Constructing a fault-tolerant quantum computer is a daunting task. Given any design, it is possible to determine the maximum error rate of each type of component that can be tolerated while still permitting arbitrarily large-scale quantum computation. It is an underappreciated fact that including an appropriately designed mechanism enabling long-range qubit coupling or transport substantially increases the maximum tolerable error rates of all components. With this thought in mind, we take the superconducting flux qubit coupling mechanism described by Plourde et al. [Phys. Rev. B 70, 140501(R) (2004)] and extend it to allow approximately 500MHz coupling of square flux qubits, $50\phantom{\rule{0.3em}{0ex}}\ensuremath{\mu}\mathrm{m}$ a side, at a distance of up to several millimeters. This mechanism is then used as the basis of two scalable architectures for flux qubits taking into account cross-talk and fault-tolerant considerations such as permitting a universal set of logical gates, parallelism, measurement and initialization, and data mobility.
The technological development of hardware heading toward universal fault-tolerant quantum computation requires a large-scale processing unit with high performance. While fluxonium qubits are promising with high coherence and large anharmonicity, their scalability has not been systematically explored. In this work, we propose a superconducting quantum information processor based on compact high-coherence fluxoniums with suppressed crosstalk, reduced design complexity, improved operational efficiency, high-fidelity gates, and resistance to parameter fluctuations. In this architecture, the qubits are readout dispersively using individual resonators connected to a common bus and manipulated via combined on-chip RF and DC control lines, both of which can be designed to have low crosstalk. A multi-path coupling approach enables exchange interactions between the high-coherence computational states and at the same time suppresses the spurious static ZZ rate, leading to fast and high-fidelity entangling gates. We numerically investigate the cross resonance controlled-NOT and the differential AC-Stark controlled-Z operations, revealing low gate error for qubit-qubit detuning bandwidth of up to 1 GHz. Our study on frequency crowding indicates high fabrication yield for quantum processors consisting of over thousands of qubits. In addition, we estimate low resource overhead to suppress logical error rate using the XZZX surface code. These results promise a scalable quantum architecture with high performance for the pursuit of universal quantum computation.
Efficient quantum error correction and fault-tolerant quantum computing require scalable, high-fidelity long-range connectivity. In neutral-atom quantum computers, this is commonly achieved through atom transport, but shuttling introduces latency and motional heating that worsen with system size. Here, we introduce a neutral-atom architecture based on static atomic buses, in which auxiliary mediator atoms enable long-range entangling operations without qubit transport. The architecture naturally supports long-range stabilizer measurements in high-rate LDPC codes and transversal logical gates between neighboring surface-code patches, enabling a modular framework for efficient logical memories, Clifford computation, and magic-state distillation. To realize these capabilities, we co-design optimal-control protocols for bus-mediated controlled-Z gates that incorporate both microscopic neutral-atom dynamics and architectural constraints. We obtain smooth bus-mediated gates with fidelities approaching 99.9% and durations of a few hundred nanoseconds by combining time-optimal control with interaction-flatness and robustness constraints. Large-scale simulations of quantum error correction and logical entangling operations between neighboring surface-code patches predict more than an order-of-magnitude improvement in logical error rates compared with atom-shuttling architectures under realistic noise. The architecture achieves logical gate times of approximately 100 us and quantum-error-correction cycle times of about 1 ms for code distances d<12. These results establish static atomic buses as a practical alternative to atom shuttling for scalable fault-tolerant neutral-atom quantum computing.
Maintaining or even improving gate performance with growing numbers of parallel controlled qubits is a vital requirement for fault-tolerant quantum computing.For superconducting quantum processors, though isolated one-or two-qubit gates have been demonstrated with high fidelity, implementing these gates in parallel commonly shows worse performance.Generally, this degradation is attributed to various crosstalks between qubits, such as quantum crosstalk due to residual inter-qubit coupling.An understanding of the exact nature of these crosstalks is critical to figuring out respective mitigation schemes and improved qubit architecture designs with low crosstalk.Here we give a theoretical analysis of quantum crosstalk impact on simultaneous gate operations in a qubit architecture, where fixed-frequency transmon qubits are coupled via a tunable bus, and sub-100-ns controlled-Z (CZ) gates can be realized by applying a baseband flux pulse on the bus.Our analysis shows that for microwave-driven single-qubit gates, the dressing from the qubit-qubit coupling can cause non-negligible cross-driving errors when qubits operate near frequency collision regions.During CZ gate operations, although unwanted nearest-neighbor interactions are nominally turned off, sub-MHz parasitic next-nearest-neighbor interactions involving spectator qubits can still exist, causing considerable leakage or control error when one operates qubit systems around these parasitic resonance points.To ensure high-fidelity simultaneous operations, a request could be raised to figure out a better way to balance the gate error from target qubit systems themselves and the error from nonparticipating spectator qubits.Overall, our analysis suggests that towards useful quantum processors, the qubit architecture should be examined carefully in the context of high-fidelity simultaneous gate operations in a scalable qubit lattice.
The path toward practical superconducting quantum processors requires the integration of a large number of high-performance qubits. Modular architectures could offer a way to address the scaling limitations of monolithic designs by partitioning a large quantum processor into physically separated modules, or chiplets, linked through long-range interconnects. In this context, although fluxonium qubits have emerged as a compelling platform for quantum computing due to their long coherence times and high-fidelity gates, existing coupling schemes remain restricted to qubits in close proximity on a single chip. This limitation inherently precludes the long-range interconnects essential for modular integration. In this work, we propose a long-range tunable coupler designed to interconnect fluxonium qubits separated by more than one centimeter, thereby supporting the realization of modular fluxonium quantum processors. Under realistic assumptions, the proposed coupler has the potential to achieve inter-module two-qubit gate performance, specifically sub-100-ns gates with intrinsic errors below 10−4, comparable to that of intra-module (intra-chiplet) gates, while enabling modular integration with low quantum crosstalk, a key requirement for scalable systems. We further discuss the integration of this coupler into modular fluxonium lattices and explore its feasibility for achieving the higher connectivity and longer coupling range required for complex quantum error correction codes. This work could contribute to the development of large-scale fluxonium quantum processors by bridging their demonstrated potential with modular scalability.
The principles of fault tolerance In this chapter we will consider some of the practical difficulties in building a large-scale quantum computing device. This discussion relies heavily upon the prior chapters that introduced faulttolerant quantum computation. Assuming that fault tolerance is possible allows us to focus on the physical realization of these ideas with a few specific examples. Before going into detail, we review the governing ideas behind any fault-tolerant architecture. These are the necessary components that we analyze in this chapter: good quantum memory, high-fidelity quantum operations, long-range quantum gates, and highly parallel operation, such that error correction in different sections of the device can be accomplished at the same time. While a wide variety of potential implementations may be possible, the goal of a fault-tolerant architecture is not only to be scalable, i.e., to be able to run an arbitrarily large computation with at most polynomial overhead [S95, S96e], but also to be as efficient as possible. Efficiency in this context means using the fewest physical resources (quantum bits, time, control operations) necessary to accomplish the desired computation [S03b]. From this perspective, the recipe for fault tolerance is well established. First, we need to identify what quantum operations are available for the various quantum bits at our disposal. Developing error models for these operations forms the bulk of this chapter. Important questions about operations include noise, implementation time, and bandwidth (how many such operations may be performed in parallel).