Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Proceedings of the IEICE General Conference

C-8-4 Demonstration of Single-Flux-Quantum Circuits Based on 20-kA/cm^2 Process

Misaki Kouzaka, Yuma Kita, Masamitsu Tanaka, Akira Fujimaki, Shuichi Nagasawa, Mutsuo Hidaka

Published Mar 4, 2014• 0 citations
OpenAlex

Related papers

Operations of Single Flux Quantum Circuits Based on 40-kA/cm^2 Process

Kouketsu Tomohito, Akaike Hiroyuki, Fujimaki Akira +4 more

IEICE Technical Report; IEICE Tech. Rep.•Jul 15, 2010•0 citations

Demonstration of a 120 GHz single-flux-quantum shift register circuit based on a 10 kA cm−2Nb process

Hiroyuki Akaike, Takahiro Yamada, Akira Fujimaki +5 more

Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm −2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters β c of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.

Superconductor Science and Technology•Mar 16, 2006•33 citations

Design and demonstration of fundamental logic circuits based on a single-flux-quantum gate with a resettable latch

Naoki Takeuchi, A. Akahori, N. Mori +4 more

We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.

IEEE Transactions on Applied Superconductivity•Mar 1, 2001•0 citations

Recent Progress in Rapid-Single-Flux-Quantum Circuits

Akira Fujimaki, Takahiro Yamada, Masamitsu Tanaka +4 more

Advances in science and technology•Oct 1, 2006•1 citation

High-speed demonstration of an output interface driver for single-flux quantum systems

N. Harada, Akira Yoshida, Naoki Yokoyama

The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.

IEEE Transactions on Applied Superconductivity•Sep 1, 2002•9 citations

Single-flux quantum electronics

Kiyotaka Nakajima

Taylor & Francis eBooks•Jan 1, 1998•0 citations
Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm −2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters β c of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.
We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.
The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm/sup 2/ standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.