Rapid Single Quantum Flux (RFSQ) Logic

K. K. Likharev

Pascal Febvre

Bicong Weng, Xiaoping Gao, Jie Ren +4 more

Gleb Krylov, Tahereh Jabbari, Eby G. Friedman

Abirami G, Punithavathy Mohan

Rapid Single Flux Quantum (RSFQ) is a digital electronic technology that uses superconducting devices to process the digital signals. The information is stored inthe form of magnetic flux quanta, in RFSQ logic. Resistor-free approach to dc biasing of RSFQ logical circuits are known as Energy-efficient Rapid Single FluxQuantum (ERSFQ) that does not use bias resistors. The ERSFQ logic is to eliminate the static power loss of RSFQ by replacing bias resistors with set of inductors and current-limiting Josephson junction. Traditionally, the ERSFQ logical circuit is designed in this paper. In the ERSFQ architecture, numbers of half adders are used to design this structure. The main disadvantage of ERFSQ structure, the number of transistor count is increased. In order to reduce this problem, ERFSQ based GDI (Gate Diffusion Input) technique is proposed in this paper. The schematic circuit of proposed ERSFQ based GDI technique is designed by using Tanner EDA tool.

Samuel Intiso

Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) is a digital technology characterized by high speed, low power consumption and low operational temperatures. RSFQ is attractive for many applications and in particular for high frequency Digital Signal Processing (DSP) and for digital control of mK devices like superconducting qubits. Due to the 30 GHz clock speed, RSFQ DSP could be used to implement a Successive Interference Canceller for multi-user detection in a 3G wireless systems. The being developed DSP consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory and external semiconductor memory.The first part of this thesis is focusing on architecture and implementation of the hierarchical CMOS-RSFQ hybrid memory for the RSFQ DSP. The architecture ofthe RSFQ cache is optimized in order to reach the highest speed and reliable data communication with CMOS memory. Aspects of block synchronization betweenthe RSFQ cache and the RSFQ digital core are discussed and solved using a new developed RSFQ gate, C3. For design of different components of the DSP, a designapproach based on validated VHDL models is proposed and experimentally verified.The second part of this thesis is focusing on the design oflow-dissipative RSFQ circuits for interface to the superconducting qubits. Power dissipation ofRSFQ circuits is minimized. A low-temperature thermal model of resistively shunted Josephsonjunctions is developed and applied to optimize the shape of the shunt resistors in order to reduce their electron temperature. Depending on the available fabricationprocess the lowest noise temperature of RSFQ circuit can be in the range from 90 mK to 180 mK.