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IEEE International Symposium on Multiple-Valued Logic (ISMVL)

Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits

Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille

Published May 1, 2016• 26 citations
Publisher

Abstract

The rapid advances of quantum technologies are opening up new challenges, of which, protecting quantum states from errors is a major one. Among quantum error correction schemes, the surface code is emerging as a natural choice with high-fidelity quantum gates reported for experimental platforms. Surface codes also necessitate the quantum gates to be formed with strict nearest neighbour coupling. State-of-the-art-reversible logic synthesis techniques for quantum circuit implementation do not ensure the logic gates to be formed in a nearest neighbor fashion, and this is handled as a post processing optimization by the insertion of swap gates. In this paper, we propose, for the first time, the inclusion of nearest neighbourhood criteria in a widely used ancilla free reversible logic synthesis method. Experimental results show that this method easily outperforms the earlier two step techniques in terms of gate count without any runtime overhead.

DOI
10.1109/ismvl.2016.54

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The rapid advances of quantum technologies are opening up new challenges, of which, protecting quantum states from errors is a major one. Among quantum error correction schemes, the surface code is emerging as a natural choice with high-fidelity quantum gates reported for experimental platforms. Surface codes also necessitate the quantum gates to be formed with strict nearest neighbour coupling. State-of-the-art-reversible logic synthesis techniques for quantum circuit implementation do not ensure the logic gates to be formed in a nearest neighbor fashion, and this is handled as a post processing optimization by the insertion of swap gates. In this paper, we propose, for the first time, the inclusion of nearest neighbourhood criteria in a widely used ancilla free reversible logic synthesis method. Experimental results show that this method easily outperforms the earlier two step techniques in terms of gate count without any runtime overhead.
With the advancement of technological footprints, high-end computation techniques, like quantum computation, have made significant progress in the design industry. Although quantum computation has proved itself as the next-generation computing paradigm, it is facing several design challenges, and one such design issue is in the form of the Nearest Neighbour (NN)t. This much-talked NN property demands the qubits in operating quantum gates to be adjacent, and a circuit should satisfy this NN property to be eligible for implementation. Considering the importance of NN enforcement in implementing circuits, we introduce a synthesis approach for the efficient transformation of reversible circuits to equivalent LNN representations. Our main focus in this work is to minimize the use of SWAP gates in designing NN-satisfied MCT-based reversible circuits. Towards transforming input circuits to LNN architecture, we have exploited a template matching scheme followed by two-qubit reordering policies, global and local, to improve the NN designs and reduce SWAP utilization. In finding the global solution, here we have used a dynamic programming algorithm where the initial order of qubit lines gets changed, while a heuristic-based SWAP placement function is used for finding a local qubit order sequence. The proposed synthesis workflow has been tested over an extensive set of benchmark functions, and comparison with the reported design approaches showed a substantial reduction in cost parameters.
Linear Nearest Neighbor (LNN) synthesis in reversible circuits has emerged as an important issue in terms of technological implementation for quantum computation. The objective is to obtain a LNN architecture with minimum gate cost. As achieving optimal synthesis is a hard problem, heuristic methods have been proposed in recent literature. In this work we present a graph partitioning based approach for LNN synthesis with reduction in circuit cost. In particular, the number of SWAP gates required to convert a given gate-level quantum circuit to its equivalent LNN configuration is minimized. Our algorithm determines the reordering of indices of the qubit line(s) for both single control and multiple controlled gates. Experimental results for placing the target qubits of Multiple Controlled Toffoli (MCT) library of benchmark circuits show a significant reduction in gate count and quantum gate cost compared to those of related research works.
The quest of achieving higher computing performance is driving the research on quantum computing, which is reporting new milestones almost on a daily basis. For practical quantum circuit design, fault tolerance is an essential condition. This is achieved by mapping the target functions into the Clifford+T group of elementary quantum gates. Furthermore, the application of error-correcting codes in quantum circuits requires the quantum gates to be formed between adjacent Qubits. In this work, we improve the state-of-the-art quantum circuit design by addressing both of the above challenges. First, we propose a novel mapping of Multiple-Control Toffoli (MCT) gates to Clifford+T group gates, which achieves lower gate count compared to earlier work. Secondly, we show a generic way to convert any Clifford+T circuit into a nearest neighbor one. We validate the efficacy of our approach with detailed experimental studies.
Real quantum computing technologies have different restrictions and constraints which need to be considered during circuit synthesis. In certain technologies, only physically adjacent qubits can interact. It is common to use a pair of SWAP gates to bring the control and target qubits of any quantum gate to adjacent lines and maintain correct circuit functionality. This paper introduces a new method to synthesize linear nearest neighbor quantum circuit on the base of the analysis of quantum state in circuit. For all 3-qubit quantum circuit, experimental results shows that our algorithm can reduce the quantum cost by approximately 30% on average compared with one recent proposed method.
In the present era of computation, quantum computing may offer a new direction as it allows to solve certain problems significantly faster than classical solutions. But it also has been found that there are several constrains in performing a successful realization of quantum circuits. One such constraint is the nearest neighbor (NN) criterion which states that qubits which interact with each other have to be adjacent. Motivated by this objective, in this work we propose a linear qubit placement technique that effectively rearranges the qubits and transforms quantum circuits to improved NN-based designs by inserting SWAPs. Furthermore, for placing these SWAPs in appropriate positions, we implemented a look-ahead strategy that considers the effect of the rest of the gates and computes a corresponding impact value which guides the insertion of the SWAP gates. To this extent, we consider three different strategies to evaluate the corresponding "look-ahead effects" and their influence on existing gates. At the end of this work, we have evaluated the developed methodology over a wide range of benchmarks and compared the results with existing related works. In this comparison, we have seen that the proposed technique outperforms the related works and provides substantial reductions in SWAP overhead.
We present a logic synthesis method based on lattices that realize quantum arrays in One-Dimensional Ion Trap technology. This means that all gates are built from 2x2 quantum primitives that are located only on neighbor qubits in a one-dimensional space (called also vector of qubits or Linear Nearest Neighbor (LNN) architecture). The Logic circuits designed by the proposed method are realized only with 3*3 Toffoli, Feynman and NOT quantum gates and the usage of the commonly used multi-input Toffoli gates is avoided. This realization method of quantum circuits is different from most of reversible circuits synthesis methods from the literature that use only high level quantum cost based on the number of quantum gates. Our synthesis approach applies to both standard and LNN quantum cost models. It leads to entirely new CAD algorithms for circuit synthesis and substantially decreases the quantum cost for LNN quantum circuits. The drawback of synthesizing circuits in the presented LNN architecture is the addition of ancilla qubits.