Error correction and fault-tolerant computation

Theerapat Tansuwannont

In quantum computation, errors in a quantum circuit arising from its interaction with the environment is one of the biggest obstacles to building large-scale quantum computers. One way to deal with such errors is using fault-tolerant error correction (FTEC), a procedure which suppresses error propagation in a quantum circuit, together with other fault-tolerant gadgets for quantum computation to simulate a quantum circuit. However, for some platforms in which the number of physical qubits is limited, achieving a fault-tolerant simulation with very low logical error rate can be challenging since large overhead is required. \nIn this thesis, flag and weight parity techniques for FTEC which use only small number of ancillas are studied. The flag technique uses a few ancillas in circuits for syndrome measurement to detect high-weight errors arising from a few faults, while the weight parity technique uses weight parities and syndromes of errors to determine whether they are logically equivalent. The concepts of these two techniques can lead to the notion of distinguishable fault set, the central idea for the fault-tolerant protocol development in this thesis. In addition, fault-tolerant protocols for two families of codes are constructed: an FTEC protocol for the [[49,1,9]] concatenated Steane code which can correct up to 3 faults and uses 2 ancillas, and protocols for fault-tolerant quantum computation on capped color codes which require 1, 1, and 2 ancillas for the codes of distance 3, 5, and 7. The concept of distinguishable fault set also leads to a generalization of the definitions of fault-tolerant gadgets which give more flexibility when designing fault-tolerant protocols.

Tzvetan S. Metodi, Frederic T. Chong

Ivan B. Djordjević

Lingling Lao, Carmen G. Almudéver

Fault-tolerant (FT) computation by using quantum error correction (QEC) is essential for realizing large-scale quantum algorithms. Devices are expected to have enough qubits to demonstrate aspects of fault tolerance in the near future. However, these near-term quantum processors will only contain a small amount of noisy qubits and allow limited qubit connectivity. Fault-tolerant schemes that not only have low qubit overhead but also comply with geometrical interaction constraints are therefore necessary. In this work, we combine flag fault tolerance with quantum circuit mapping, to enable an efficient flag-bridge approach to implement FT QEC on near-term devices. We further show an example of performing the Steane code error correction on two current superconducting processors and numerically analyze their performance with circuit level noise. The simulation results show that the QEC circuits that measure more stabilizers in parallel have lower logical error rates. We also observe that the Steane code can outperform the distance-3 surface code using flag-bridge error correction. In addition, we foresee potential applications of the flag-bridge approach such as FT computation using lattice surgery and code deformation techniques.

V. Karthick, M. Ramkumar Prabhu, P. Nancy +2 more

Fault-tolerant quantum error correction (FTQEC) is pivotal for ensuring the reliability and scalability of quantum computers, which harness quantum mechanics principles. This paper presents a comprehensive analysis of FTQEC methodologies, integrating theoretical investigations, experimental validations, error correction capabilities, and simulation comparisons. Theoretical frameworks reveal high error correction capabilities, with success rates ranging from 0.88 to 0.95 and significant error rate reductions of up to 98%. Experimental validations across diverse quantum hardware platforms demonstrate promising results, with high success rates and notable error correction efficiency, albeit challenges in scalability. Analysis of error correction capabilities highlights robustness against errors and preservation of qubits integrity during error correction procedures. Simulation comparisons further validate the efficacy of FTQEC protocols, showing significant improvements in error rate reduction and gate fidelity. However, scalability and resource overhead remain concerns, necessitating further research for efficient and scalable FTQEC protocols. Overall, this study contributes to the understanding and advancement of fault-tolerant quantum error correction, crucial for realizing the transformative potential of quantum computing technology.

Ivan B. Djordjević